原文档156-168页简易翻译

由于译者英文水平实在是有限，所以全部照搬翻译器内容。图表部分未包含在其中，请对照原文查阅。英文部分来自Intel® 82801AA (ICH) and Intel® 82801AB (ICH0) I/O Controller Hub Datasheet。中文部分翻译来自彩云小译（翻译器360翻译）。

译者至强2023-3-12

5.17 ICH AC’97 2.1 Functional Description

ICH AC’972.1功能描述

This section describes the AC-link interface including an overview of the AC-link implementation

in the ICH and a detailed feature list of what is supported. Also included in this section is a

recommended feature list for AC’97 codecs. These are features that Intel recommends for a codec

designed for the ICH AC’97 controller.

本节描述AC-link 接口，包括 ICH 中 AC-link 实现的概述和所支持内容的详细特性列表。本节还推荐了 AC’97编解码器的特性列表。这些是 Intel 推荐的用于 ICH AC’97控制器的编解码器的特性。

For further information on the operation of the AC-link protocol, refer to the AC’97 specification.

References to AC’97 in this document refer to the AC’97 2.1 specification.

有关AC 链路协议操作的进一步信息，请参考 AC’97规范。本文档中对 AC’97的引用参见 AC’972.1规范。

Note: Poor performing PCI devices that cause long latencies (numerous retries) to CPU-to-PCI locked

cycles may starve isochronous transfers between USB or AC’97 devices and memory. This will

result in overrun or underrun, causing reduced quality of the isochronous data (e.g., audio).

注意: 表现不佳的 PCI 设备会导致 CPU-to-PCI 锁定周期的长延迟(大量重试) ，可能会导致 USB 或 AC’97设备与内存之间的同步传输受阻。这将导致溢出或溢出，从而降低等时数据(例如，音频)的质量。

The ICH supports the following features:

• Independent PCI functions for audio and modem

• Independent channels for PCM in and PCM out, microphone in

• Left and right audio channels

• Single modem line

• 16 bit sample resolution

• Multiple sample rates

• 16 GPIOs

• Dual codec configuration with two SDIN pins

Table 5-81 shows a detailed list of features supported by the ICH AC’97 digital controller.

ICH 支持以下功能: •独立的音频和调制解调器 PCI 功能•独立的 PCM 输入和输出通道，麦克风输入和右侧音频通道•单调制解调器线路•16位采样分辨率•多样化采样率•16 GPIO •双编解码器配置与两个 SDIN pinsTable 5-81显示了 ICH AC’97数字控制器支持的功能的详细列表。

Table 5-81. Featured Supported by ICH

表5-81. ICH 支持的特点

System Interface

系统接口

• Isochronous low latency bus master memory interface

• Scatter/gather support for word-aligned buffers in memory

(all mono or stereo 16-bit data types are supported, no 8-bit data types are supported)

• Data buffer size in system memory from 3 to 65535 samples per input

• Data buffer size in system memory from 0 to 65535 samples per output

• Independent PCI audio and modem functions with configuration and IO spaces

• AC’97 codec registers are shadowed in system memory via driver (not PCI IO space)

• AC’97 codec register accesses are serialized via semaphore bit in PCI IO space (new

accesses are not allowed while a prior access is still in progress)

•等时低延迟总线主存接口。•分散/收集支持内存中的字对齐缓冲区(支持所有单位或立体16位数据类型，不支持8位数据类型)。* 系统内存中的数据缓冲区大小从每个输入3个样本到65535个样本。* 系统内存中的数据缓冲区大小从每个输出0到65535个样本。•具有配置和 IO 空间的独立 PCI 音频和调制解调器功能。• AC’97编解码寄存器通过驱动程序(而非 PCI IO 空间)隐藏在系统内存中。AC’97编解码器寄存器访问是通过 PCI IO 空间中的信号量位序列化的(如果之前的访问仍在进行中，则不允许新的访问)。

Power

Management

电力管理

• Power management via ACPI control methods

Support for audio states: D0, D2, D3hot, D3cold

Support for modem states: D0, D3hot, D3cold

• SCI event generation for PCI modem function with wake-up from D3cold

• Independent codec D3 w/ Link down event, synchronized via two bit semaphore (in

PCI IO Space)

通过ACPI 控制方法进行电源管理。对音频状态的支持: D0，D2，D3hot，D3coldSupport 对调制解调器状态的支持: D0，D3hot，D3cold • SCI 事件生成用于从 D3cold 唤醒 PCI 调制解调器功能。•独立编解码器 D3w/Link 下行事件，通过两位信号量(在 PCI IO 空间)同步

PCI Audio

Function

PCI 音频功能

• Read/write access to audio codec registers 00h-3Ah and vendor registers 5Ah–7Eh

• 16-bit stereo PCM output, up to 48 kHz (L,R channels on slots 3,4)

• 16-bit stereo PCM input, up to 48 kHz (L,R channels on slots 3,4)

• 16-bit mono mic in w/ or w/o mono mix, up to 48 kHz (L,R channel, slots 3,4) (mono

mix supports mono hardware AEC reference for speakerphone)

• 16-bit mono PCM input, up to 48 kHz from dedicated mic ADC (slot 6)

(supports speech recognition or stereo hardware AEC ref for speakerphone)

• During cold reset AC_RST# is held low until after POST and software deassertion of

AC_RST# (supports passive PC_BEEP to speaker connection during POST)

•对音频编解码器寄存器00h-3Ah 和供应商寄存器5Ah-7Eh 的读/写访问。•16位立体声 PCM 输出，最高48kHz (插槽3、4上的 L、 R 通道)。•16位立体声 PCM 输入，最高48kHz (插槽3、4上的 L、 R 通道)。• W/或 W/o 单声道组合的16位单声道麦克风，最高可达48kHz (L，R 通道，插槽3,4)(单声道组合支持扬声器的单声道硬件 AEC 参考)。•16位单片机输入，从专用麦克风 ADC (插槽6)输入高达48千赫(支持语音识别或扬声器的立体声硬件 AEC 参考)。在冷重置期间 AC _ RST # 保持低位，直到 POST 和 AC _ RST # 的软件解除断言(在 POST 期间支持被动 PC _ BEEP 到扬声器连接)。

PCI Modem

function

PCI 调制解调器功能

• Read/write access to modem codec registers 3Ch-58h and vendor registers 5Ah–7Eh

• 16-bit mono modem line1 output and input, up to 48 kHz (slot 5)

• Low latency GPIO[15:0] via hardwired update between slot 12 and PCI IO register

• Programmable PCI interrupt on modem GPIO input changes via slot 12 GPIO_INT

• SCI event generation on primary or secondary SDIN wake-up signal

•对调制解调器编解码器寄存器3Ch-58h 和供应商寄存器5Ah-7Eh 的读/写访问。•16位单调制解调器线路1的输出和输入，最高频率为48kHz (插槽5)。•通过在插槽12和 PCI IO 寄存器之间的硬连线更新实现低延迟 GPIO [15:0]。•通过插槽12 GPIO _ INT 改变调制解调器 GPIO 输入的可编程 PCI 中断。•基于一级或二级 SDIN 唤醒信号的 SCI 事件生成。

AC-link

交流电

• AC’97 2.1 compliant AC-link interface

• Variable sample rate output support via AC’97 SLOTREQ protocol (slots 3,4,5)

• Variable sample rate input support via monitoring of slot valid tag bits (slots 3,4,5,6)

• 3.3 V digital operation meets AC’97 2.1 DC switching levels

• AC-Link IO driver capability meets AC‘97 2.1 dual codec specifications

• Codec register status reads must be returned with data in the next AC-link frame, per

AC’97 2.1 spec.

‧符合 AC’972.1标准的 AC-link 接口。•通过 AC’97 SLOTREQ 协议支持可变采样率输出(插槽3,4,5)。•通过监控插槽有效标签位(插槽3、4、5、6)提供可变采样率输入支持。•3.3 V 数码操作符合 AC’972.1 DC 开关水平。• AC-Link IO 驱动程序功能符合 AC’972.1双编解码器规格。•根据 AC’972.1规范，编解码器寄存器状态读数必须与下一个 AC 链路帧中的数据一起返回。

Multiple Codec

多重解码器

• Dual codec addressing: All AC’97 codec register accesses are addressable to codec

ID 00 (primary) or codec ID 01 (secondary)

• Dual codec receive capability via primary and secondary SDIN pins

(primary, secondary SDIN frames are internally validated, synch’d, and OR’d)

•双重编解码器寻址: 所有 AC’97编解码器寄存器访问都可以寻址到编解码器 ID 00(主)或编解码器 ID 01(辅)。双编解码器通过主要和次要 SDIN 引脚接收能力(主要，次要 SDIN 帧内部验证，同步和 OR’d)。

Note that throughout this document, references to D31:F5 indicate that the audio function exists in

PCI device 31, function 5. References to D31:F6 indicate that the modem function exists in PCI

device 31, function 5.

注意，在本文档中，对D31: F5的引用表明音频功能存在于 PCI 设备31，功能5中。对 D31: F6的引用表明调制解调器功能存在于 PCI 设备31，功能5中。

Figure 5-17. ICH Based AC’97 2.1

图5-17基于 AC’972.1的 ICH

5.17.1 AC-link Overview

5.17.1交流连结概览

The ICH is an AC’97 2.1 compliant controller that communicates with companion codecs via a

digital serial link called the AC-link. All digital audio/modem streams and command/status

information is communicated over the AC-link.

The AC-link is a bi-directional, serial PCM digital stream. It handles multiple input and output data

streams, as well as control register accesses, employing a time division multiplexed (TDM)

scheme. The AC-link architecture provides for data transfer through individual frames transmitted

in a serial fashion. Each frame is divided into 12 outgoing and 12 incoming data streams, or slots.

The architecture of the ICH AC-link allows a maximum of two codecs to be connected.

Figure 5-18 shows a two codec topology of the AC-link for the ICH in a serial fashion.

ICH 是一个 AC’972.1兼容控制器，通过一个称为 AC-link 的数字串行链路与同伴编解码器进行通信。所有数字音频/调制解调器流和命令/状态信息通过交流链路传输。交流链路是一个双向的，串行 PCM 数字流。它处理多个输入和输出数据流，以及控制寄存器访问，采用时分多路复用(TDM)方案。交流链路结构提供了通过串行方式传输的单个帧进行数据传输。每个帧分为12个传出数据流和12个传入数据流或插槽。ICH AC-link 的体系结构允许最多连接两个编解码器。图5-18以串行方式显示了 ICH 的 AC 链路的两个编解码器拓扑。

Figure 5-18. AC’97 2.1 Controller-Codec Connection

图5-18. AC’972.1控制器-编解码器连接

The AC-link consists of a five signal interface between the controller and codec. Table 5-82

indicates the AC-link signal pins on the ICH and their associated power wells.

交流链路由控制器和编解码器之间的五个信号接口组成。表5-82显示了 ICH 及其相关电源井上的交流连接信号引脚。

Table 5-82. AC’97 Signals

表5-82 AC’97信号

NOTE: Power well voltage levels are 3.3V

注意: 电源井电压等级为3.3 V

ICH core well outputs may be used as strapping options for the ICH, sampled during system reset.

These signals may have weak pullups/pulldowns; however, this will not interfere with link

operation. ICH inputs integrate weak putdowns to prevent floating traces when a secondary codec

is not attached. When the Shut Off bit in the control register is set, all buffers will be turned off and

the pins will be held in a steady state, based on these pullups/pulldowns.

ICH 核心井输出可用作 ICH 的捆绑选项，在系统重置期间取样。这些信号可能有弱上拉/下拉; 但是，这不会干扰链接操作。ICH 输入集成了弱输出，以防止在没有附加辅助编解码器时出现浮动跟踪。当控制寄存器中的关闭位被设置，所有的缓冲区将被关闭，引脚将被保持在一个稳定的状态，基于这些上拉/下拉。

BIT_CLK is fixed at 12.288 MHz and is sourced by the primary codec. It provides the necessary

clocking to support the twelve 20-bit time slots. AC-link serial data is transitioned on each rising

edge of BIT_CLK. The receiver of AC-link data samples each serial bit on the falling edge of

BIT_CLK.

BIT _ CLK 固定在12.288 MHz，由主编解码器来源。它提供了必要的时钟来支持12个20位时隙。交流链路串行数据在 BIT _ CLK 的每个上升边上进行转换。交流链路数据的接收机对 BIT _ CLK 下降沿上的每个串行位进行采样。

Synchronization of all AC-link data transactions is signaled by the AC’97 controller via the

AC_SYNC signal, as shown in Figure 5-19. The primary codec drives the serial bit clock onto the

AC-link, which the AC’97 controller then qualifies with the AC_SYNC signal to construct data

frames. AC_SYNC, fixed at 48 KHz, is derived by dividing down BIT_CLK. AC_SYNC remains

high for a total duration of 16 BIT_CLKs at the beginning of each frame. The portion of the frame

where AC_SYNC is high is defined as the tag phase. The remainder of the frame where AC_SYNC

is low is defined as the data phase. Each data bit is sampled on the falling edge of BIT_CLK.

AC’97控制器通过 AC _ SYNC 信号发出所有 AC-link 数据事务的同步信号，如图5-19所示。主编解码器将串行位时钟驱动到 AC 链路上，AC’97控制器通过 AC _ SYNC 信号对 AC’97链路进行限定，以构造数据帧。AC _ SYNC，固定在48KHz，通过除以 BIT _ CLK 得到。AC _ SYNC 在每帧开始时总共保持16个 BIT _ CLK 的高值。帧中 AC _ SYNC 高的部分被定义为标记阶段。AC _ SYNC 较低的帧的其余部分被定义为数据阶段。每个数据位在 BIT _ CLK 的下降边采样。

Figure 5-19. AC-link Protocol

图5-19交流链路协议

The ICH has two SDIN pins allowing a single or dual codec configuration. When two codecs are

connected, the primary and secondary codecs can be connected to either SDIN line; however, it is

recommended that the primary codec be attached to SDIN [0]. The ICH does not distinguish

between primary and secondary codecs on its SDIN[1:0] pins; however, the registers do distinguish

between SDIN[0] and SDIN[1] for wake events, etc. The primary codec can be an AC

(audio codec), MC (modem codec), or AMC (audio/modem codec) device. The secondary codec

can only be an MC device.

Valid codec configurations include the following:

• AC (Primary)

• MC (Primary)

• AC (Primary) + MC (Secondary)

• AMC (Primary)

The ICH does not support optional test modes as outlined in the AC’97 specification.

ICH 有两个 SDIN 引脚，允许单个或双重编解码器配置。当两个编解码器连接时，主编解码器和次编解码器可以连接到任一 SDIN 线; 但是，建议将主编解码器连接到 SDIN [0]。ICH 在其 SDIN [1:0]引脚上不区分主编解码器和次级编解码器; 然而，寄存器对于唤醒事件等确实区分了 SDIN [0]和 SDIN [1]。主编解码器可以是 AC (音频编解码器)、 MC (调制解调器编解码器)或 AMC (音频/调制解调器编解码器)设备。次级编解码器只能是 MC 设备。有效的编解码器配置包括以下内容:。‧管委会(小学)。‧ AC (小学) + MC (中学)。‧资产管理公司(小学)。ICH 不支持 AC’97规范中概述的可选测试模式。

5.17.2 AC-link Output Frame (SDOUT)

A new audio output frame begins with a low to high transition of AC_SYNC. AC_SYNC is

synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of

BIT_CLK, the codec samples the assertion of AC_SYNC. This falling edge marks the time when

both sides of AC-link are aware of the start of a new frame. On the next rising edge of BIT_CLK,

the ICH transitions SDOUT into the first bit position of slot 0, or the valid frame bit. Each new bit

position is presented to the AC-link on a rising edge of BIT_CLK and subsequently sampled by the

codec on the following falling edge of BIT_CLK. This sequence ensures that data transitions and

subsequent sample points for both incoming and outgoing data streams are time aligned.

The output frame data phase corresponds to the multiplexed bundles of all digital output data

targeting codec DAC inputs and control registers. Each output frame supports up to twelve

outgoing data time slots. The ICH generates 16-bit samples and, in compliance with the AC’97

specification, pads the 4 least significant bits of valid slots with zeros.

The output data stream is sent with the most significant bit first and all invalid slots are stuffed with

zeros. When mono audio sample streams are output from the ICH, software must ensure both left

and right sample stream time slots are filled with the same data.

5.17.2 AC-link 输出帧(SDOUT)一个新的音频输出帧以 AC _ SYNC 的低到高转换开始。AC _ SYNC 与 BIT _ CLK 的上升边同步。在紧随其后的 BIT _ CLK 下降沿上，编解码器对 AC _ SYNC 的断言进行采样。这个下降的边缘标志着时间，当双方的交流链接是意识到开始一个新的框架。在 BIT _ CLK 的下一个上升边缘，ICH 将 SDOUT 转换为槽0的第一个位位置或有效帧位。在 BIT _ CLK 的上升边上给出每个新的比特位置给 AC 链路，然后在 BIT _ CLK 的下降边上由编解码器采样。这个序列确保传入和传出数据流的数据转换和随后的采样点是按时间对齐的。所述输出帧数据相对应于针对编解码器 DAC 输入和控制寄存器的所有数字输出数据的多路丛。每个输出帧支持多达12个输出数据时隙。ICH 生成16位样本，并且，按照 AC’97规范，用零填充4个最低有效位的有效槽。输出数据流首先以最高有效位发送，并且所有无效插槽都填充了零。当单音频采样流从 ICH 输出时，软件必须确保左右采样流时隙都填充了相同的数据。

Output Slot 0: Tag Phase

Slot 0 is considered the tag phase. The tag phase is a special 16 bit time slot where each bit conveys

a valid tag for its corresponding time slot within the current frame. A one in a given bit position of

slot 0 indicates that the corresponding time slot within the current frame has been assigned to a data

stream and contains valid data. If a slot is tagged invalid with a zero in the corresponding bit

position of slot 0, the ICH stuffs the corresponding slot with zeros during that slot’s active time.

Within slot 0, the first bit is a valid frame bit (slot 0, bit 15) that flags the validity of the entire

frame. If the valid frame bit is set to one, this indicates that the current frame contains at least one

slot with valid data. When there is no transaction in progress, the ICH deasserts the frame valid bit.

Note that after a write to slot 12, that slot will always stay valid, and therefore the frame valid bit

will remain set.

The next 12 bit positions of slot 0 (bits [14:3]) indicate which of the corresponding twelve time

slots contain valid data. Bits [1:0] of slot 0 are used as codec ID bits to distinguish between

separate codecs on the link.

Using the valid bits in the tag phase allows data streams of differing sample rates to be transmitted

across the link at its fixed 48 kHz frame rate. The codec can control the output sample rate of the

ICH using the SLOTREQ bits as described in the AC’97 specification.

输出槽0: 标记阶段槽0被认为是标记阶段。标记阶段是一个特殊的16位时隙，其中每个位传递当前帧内对应时隙的有效标记。在给定位置的时隙0中的时隙表示当前帧中相应的时隙已分配给数据流并包含有效数据。如果一个时隙被标记为无效，并且在时隙0的相应比特位置上有一个零，则 ICH 将在该时隙的活动时间内将相应时隙填充为零。在槽0中，第一个位是一个有效的帧位(槽0，位15) ，它标记整个帧的有效性。如果有效帧位设置为1，则表示当前帧包含至少一个带有有效数据的槽。当没有正在进行的事务时，ICH 会去断言帧的有效位。请注意，在写入槽12之后，该槽将始终保持有效，因此帧有效位将保持设置。接下来的12位位置的槽0(位[14:3])表示相应的12个时隙中的哪一个包含有效数据。插槽0的比特[1:0]用作编解码器 ID 比特，以区分链路上的不同编解码器。在标签相位中使用有效位允许不同采样率的数据流以固定的48kHz 帧速率在链路上传输。该编解码器可以使用 AC’97规范中描述的 SLOTREQ 位控制 ICH 的输出采样速率。

Output Slot 1: Command Address Port

The command port is used to control features and monitor status of AC‘97 functions including, but

not limited to, mixer settings and power management. The control interface architecture supports

up to 64 16-bit read/write registers, addressable on even byte boundaries. Only the even registers

(00h, 02h, etc.) are valid. Output frame slot 1 communicates control register address, and write/

read command information.

In the case of the split codec implementation, accesses to the codecs are differentiated by the driver

using address offsets 00h - 7Fh for the primary codec and address offsets 80h–FEh for the

secondary codec. The differentiation on the link, however, is done via the codec ID bits. See

Section 5.17.4 for further details.

输出插槽1: 命令地址端口命令端口用于控制 AC’97功能的特性和监控状态，包括但不限于混频器设置和电源管理。控制接口架构支持多达64个16位读/写寄存器，可在偶数字节边界上寻址。只有偶数寄存器(00h、02h 等)有效。输出帧槽1通信控制寄存器地址和写/读命令信息。在分割编解码器实现的情况下，对编解码器的访问由驱动程序区分，对于主编解码器使用地址偏移量00h-7Fh，对于次编解码器使用地址偏移量80h-FEh。然而，链路上的区分是通过编解码器 ID 位完成的。有关详细信息，请参阅第5.17.4节。

Output Slot 2: Command Data Port

The command data port is used to deliver 16-bit control register write data in the event that the

current command port operation is a write cycle as indicated in slot 1, bit 19. If the current

command port operation is a read, then the entire slot time stuffed with 0’s by the ICH. Bits [19:4]

contain the write data. Bits [3:0] are reserved and are stuffed with zeros.

输出插槽2: 命令数据端口命令数据端口用于在当前命令端口操作是一个写入周期(如插槽1，位19所示)的情况下传送16位控制寄存器写入数据。如果当前的命令端口操作是一个读操作，那么 ICH 将整个槽时间填充为0。位[19:4]包含写数据。比特[3:0]是保留的，并且填充了零。

Output Slot 3: PCM Playback Left Channel

Output frame slot 3 is the composite digital audio left playback stream. Typically, this slot is

composed of standard PCM (.wav) output samples digitally mixed by the host processor. The ICH

transmits sample streams of 16 bits and stuffs the remaining bits with zeros.

Data in output slots 3 and 4 from the ICH should be duplicated by software, if there is only a single

channel out.

输出插槽3: PCM 左回放通道输出帧插槽3是复合数字音频左回放流。通常，此插槽由标准 PCM (组成。由主机处理器数字混合的输出样品。ICH 传输16位的样本流，并将剩余的位填充为零。如果只有一个输出通道，ICH 输出插槽3和4中的数据应该被软件复制。

Output Slot 4: PCM Playback Right Channel

Output frame slot 4 is the composite digital audio right playback stream. Typically, this slot is

composed of standard PCM (.wav) output samples digitally mixed by the host processor. The ICH

transmits sample streams of 16 bits and stuffs the remaining bits with zeros.

Data in output slots 3 and 4 from the ICH should be duplicated by software if there is only a single

channel out.

输出插槽4: PCM 播放右通道输出帧插槽4是复合数字音频右播放流。通常，此插槽由标准 PCM (组成。由主机处理器数字混合的输出样品。ICH 传输16位的样本流，并将剩余的位填充为零。如果只有一个输出通道，ICH 输出插槽3和4中的数据应该由软件复制。

Output Slot 5: Modem Codec

Output frame slot 5 contains modem DAC data. The modem DAC output supports 16 bit

resolution. At boot time, if the modem codec is supported, the AC’97 controller driver determines

the DAC resolution. During normal runtime operation the ICH stuffs trailing bit positions within

this time slot with zeros.

输出插槽5: 调制解调器编解码器输出帧插槽5包含调制解调器 DAC 数据。调制解调器 DAC 输出支持16位分辨率。在引导时，如果支持调制解调器编解码器，则 AC’97控制器驱动程序决定 DAC 分辨率。在正常的运行时操作期间，ICH 在这个时间槽内用零填充尾随位位置。

Output Slots 6-11: Reserved

Output frame slots 6-11 are reserved and are always stuffed with 0’s by the ICH AC’97 controller.

输出插槽6-11: 预留的输出帧插槽6-11是预留的，并且总是由 ICH AC’97控制器填充0。

Output Slot 12: I/O Control

16 bits of DAA and GPIO control (output) and status (input) have been directly assigned to bits on

slot 12 to minimize latency of access to changing conditions.

The value of the bits in this slot are the values written to the GPIO control register at offset 54h and

D4h (in the case of a secondary codec) in the modem codec I/O space. The following rules govern

the usage of slot 12.

1. Slot 12 is marked invalid by default on coming out of AC-link reset, and will remain invalid

until a register write to 54h/D4h.

2. A write to offset 54h/D4h in codec I/O space will cause the write data to be transmitted on slot

12 in the next frame, with slot 12 marked valid, and the address/data information to also be

transmitted on slots 1 and 2.

3. After the first write to offset 54h/D4h, slot 12 remains valid for all following frames. The data

transmitted on slot 12 is the data last written to offset 54h/D4h. Any subsequent write to the

register will cause the new data to be sent out on the next frame.

4. Slot 12 gets invalidated after the following events: PCI reset, AC'97 cold reset, warm reset,

and hence a wake from S3, S4, or S5. Slot 12 remains invalid until the next write to offset

54h/D4h.

输出插槽12: I/O 控制16位 DAA 和 GPIO 控制(输出)和状态(输入)已被直接分配给插槽12上的位，以尽量减少访问不断变化的条件的延迟。该插槽中的位值是在调制解调器编解码器 I/O 空间中偏移54h 和 D4h (对于二级编解码器)写入 GPIO 控制寄存器的值。以下规则管理槽12的使用。1.缺省情况下，当从交流链路复位中出来时，插槽12被标记为无效，并且将一直无效，直到寄存器写入到54h/D4h。2.在编解码器 I/O 空间中偏移54h/D4h 的写操作将导致写数据在下一帧的12槽传输，12槽被标记为有效，地址/数据信息也在1槽和2槽传输。3.在第一次写入偏移量为54h/D4h 之后，槽12对于以下所有帧仍然有效。在插槽12上传输的数据是最后写入以偏移54h/D4h 的数据。随后对寄存器的任何写操作都将导致新数据在下一帧中发送出去。4.插槽12在以下事件之后失效: PCI 复位、 AC’97冷复位、暖复位，因此从 S3、 S4或 S5唤醒。在下一次写入偏移54h/D4h 之前，第12槽仍然无效。

5.17.3 AC-link Input Frame (SDIN)

There are two SDIN lines on the ICH for use with a primary and secondary codec. Each SDIN pin

can have a codec attached. Depending upon which codec (AC, MC, or AMC) is attached, various

slots will be valid or invalid. The data slots on the two inputs must be completely orthogonal

(except for the tag slot 0); that is, no two data slots at the same location will be valid on both lines.

This precludes the use of two similar codecs (e.g., two ACs or MCs) that use the same time slots.

The input frame data streams correspond to the multiplexed bundles of all digital input data

targeting the AC’97 controller. As in the case for the output frame, each AC-link input frame

consists of twelve time slots.

5.17.3交流链路输入框架(SDIN) ICH 上有两条 SDIN 线，用于主编解码器和辅助编解码器。每个 SDIN 引脚可以附加一个编解码器。根据附加的编解码器(AC、 MC 或 AMC) ，各种插槽将是有效的或无效的。两个输入上的数据槽必须是完全正交的(标记槽0除外) ; 也就是说，同一位置上的两个数据槽在两行上都不会有效。这就排除了使用两个使用相同时隙的相似编解码器(例如，两个 AC 或 MC)的可能性。输入帧数据流对应于针对 AC’97控制器的所有数字输入数据的多路复用包。与输出帧一样，每个 AC 链路输入帧由12个时隙组成。

A new audio input frame begins with a low to high transition of AC_SYNC. AC_SYNC is

synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of

BIT_CLK, the receiver samples the assertion of AC_SYNC. This falling edge marks the time when

both sides of AC-link are aware of the start of a new audio frame. On the next rising edge of

BIT_CLK, the codec transitions SDIN into the first bit position of slot 0 (codec ready bit). Each

new bit position is presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled

by the ICH on the following falling edge of BIT_CLK. This sequence ensures that data transitions

and subsequent sample points for both incoming and outgoing data streams are time aligned.

SDIN data stream must follow the AC’97 specification and be MSB justified with all non-valid bit

positions (for assigned and/or unassigned time slots) stuffed with zeros. SDIN data is sampled by

the ICH on the falling edge of BIT_CLK.

一个新的音频输入帧以AC _ SYNC 的低到高转换开始。AC _ SYNC 与 BIT _ CLK 的上升边同步。在紧随其后的 BIT _ CLK 下降边上，接收方对 AC _ SYNC 的断言进行采样。这个下降的边缘标志着时间，当双方的交流链接都意识到一个新的音频帧的开始。在 BIT _ CLK 的下一个上升边缘，编解码器将 SDIN 转换为插槽0(编解码器就绪位)的第一个位位置。在 BIT _ CLK 的一个上升边上，每个新的位置被呈现给 AC 链路，然后在 BIT _ CLK 的下降边上被 ICH 采样。这个序列确保传入和传出数据流的数据转换和随后的采样点是按时间对齐的。SDIN 数据流必须遵循 AC’97规范，并且使用填充了零的所有无效位位置(对于分配和/或未分配的时隙)对 MSB 进行合理化。SDIN 数据由 BIT _ CLK 下降沿上的 ICH 采样。

Input Slot 0: Tag Phase

Input slot 0 consists of a codec ready bit (bit 15), and slot valid bits for each subsequent slot in the

frame (bits [14:3]).

The codec ready bit within slot 0 (bit 15) indicates whether the codec on the AC-link is ready for

operation. If the codec ready bit in slot 0 is a zero, the codec is not ready for normal operation.

When the AC-link codec ready bit is a 1, it indicates that the AC-link and codec control and status

registers are in a fully operational state. The codec ready bits are visible through the Global Status

register of the ICH. Software must further probe the Powerdown Control/Status register in the

codec to determine exactly which subsections, if any, are ready.

Bits [14:3] in slot 0 indicate which slots of the input stream to the ICH contain valid data, just as in

the output frame. The remaining bits in this slot are stuffed with zeros.

输入插槽0: 标签相位输入插槽0包括一个编解码器就绪位(位15) ，以及帧中每个后续插槽的有效位(位[14:3])。插槽0(位15)内的编解码器就绪位指示 AC 链路上的编解码器是否准备就绪。如果插槽0中的编解码器就绪位为零，则该编解码器不能正常运行。当 AC 链路编解码器就绪位为1时，它表示 AC 链路和编解码器控制和状态寄存器处于完全可操作状态。编解码器就绪位可以通过 ICH 的全局状态寄存器看到。软件必须进一步探测编解码器中的 Powerdown Control/Status 寄存器，以确定哪些子节(如果有的话)准备就绪。插槽0中的比特[14:3]表示 ICH 的输入流的哪个插槽包含有效数据，就像在输出框架中一样。这个插槽中剩余的位被零填充。

Input Slot 1: Status Address Port / Slot Request Bits

The status port is used to monitor status of codec functions including, but not limited to, mixer

settings and power management.

Slot 1 must echo the control register index, for historical reference, for the data to be returned in

slot 2, assuming that slots 1 and 2 had been tagged valid by the codec in slot 0.

For multiple sample rate output, the codec examines its sample rate control registers, the state of its

FIFOs, and the incoming SDOUT tag bits at the beginning of each audio output frame to determine

which SLOTREQ bits to set active (low). SLOTREQ bits asserted during the current audio input

frame signal which output slots require data from the controller in the next audio output frame. For

fixed 48 kHz operation, the SLOTREQ bits are always set active (low) and a sample is transferred

each frame.

For multiple sample rate input, the tag bit for each input slot indicates whether valid data is present

or not.

输入插槽1: 状态地址端口/插槽请求位状态端口用于监视编解码器功能的状态，包括(但不限于)混频器设置和电源管理。插槽1必须回显控制寄存器索引，以便进行历史引用，以便在插槽2中返回数据，假设插槽1和2已被插槽0中的编解码器标记为有效。对于多采样速率输出，编解码器检查其采样速率控制寄存器、其 FIFO 的状态，以及每个音频输出帧开始处传入的 SDOUT 标签位，以确定哪些 SLOTREQ 位设置为活动(低)。在当前音频输入帧信号中断言的 SLOTREQ 位，其输出槽需要来自下一个音频输出帧中的控制器的数据。对于固定的48kHz 操作，SLOTREQ 位总是设置为活动(低) ，并且每帧传输一个样本。对于多个采样率输入，每个输入槽的标记位指示是否存在有效数据。

Table 5-83. Input Slot 1 Bit Definitions

表5-83. 输入槽1位定义

比特 描述

19 保留(设置为零)

18:12 控制寄存器索引(如果标记为无效，则填充0)

11插槽3请求: PCM 左通道 *

10插槽4请求: PCM 右通道 *

9插槽5请求: 调制解调器线路1

8:2插槽请求6-12: 未实现

1:0保留(填充0)

NOTE: *Slot 3 Request and Slot 4 Request bits must be the same value (i.e., set or cleared in tandem).

As shown in Table 5-83, slot 1 delivers codec control register read address and multiple sample rate

slot request flags for all output slots of the controller. When a slot request bit is set by the codec, the

controller returns data in that slot in the next output frame. Slot request bits for slots 3 and 4 are

always set or cleared in tandem (i.e., both are set or cleared).

When set to 1, the input slot 1 tag bit only pertains to Status Address Port data from a previous

read. SLOTREQ bits are always valid independent of the slot 1 tag bit.

Input Slot 2: Status Data Port

The status data port receives 16-bit control register read data.

Bit [19:4]: Control Register Read Data

Bit [3:0]: Reserved.

Input Slot 3: PCM Record Left Channel

Input slot 3 is the left channel input of the codec. The ICH supports 16-bit sample resolution.

Samples transmitted to the ICH must be in left/right channel order.

Input Slot 4: PCM Record Right Channel

Input slot 4 is the right channel input of the codec. The ICH supports 16-bit sample resolution.

Samples transmitted to the ICH must be in left/right channel order.

Input Slot 5: Modem Line

Input slot 5 contains MSB justified modem data. The ICH supports 16-bit sample resolution.

Input Slot 6: Optional Dedicated Microphone Record Data

Input slot 6 is a third PCM system input channel available for dedicated use by a microphone. This

input channel supplements a true stereo output that enables a more precise echo cancellation

algorithm for speakerphone applications. The ICH supports 16-bit resolution for slot 6 input.

注意: * 插槽3请求和插槽4请求位必须是相同的值(即，串联设置或清除)。如表5-83所示，插槽1为控制器的所有输出插槽提供编解码器控制寄存器读取地址和多个采样率插槽请求标志。当一个插槽请求位由编解码器设置时，控制器在下一个输出帧中返回该插槽中的数据。插槽3和4的插槽请求位始终是串联设置或清除的(也就是说，两者都是设置或清除的)。当设置为1时，输入槽1标记位仅适用于以前读取的状态地址端口数据。SLOTREQ 位始终独立于槽1标记位有效。

输入槽2: 状态数据端口状态数据端口接收16位控制寄存器读取数据。位[19:4] : 控制寄存器读取数据位[3:0] : 保留。输入插槽3: PCM Record Left ChannelInput

插槽3是编解码器的左通道输入。ICH 支持16位示例分辨率。传送至非物质文化遗产的样本必须按左/右通道顺序排列。

输入槽4: PCM 记录右通道输入槽4是编解码器的右通道输入。ICH 支持16位示例分辨率。传送至非物质文化遗产的样本必须按左/右通道顺序排列。

输入插槽5: 调制解调器线路输入插槽5包含 MSB 调制解调器数据。ICH 支持16位示例分辨率。

输入插槽6: 可选的专用麦克风记录数据输入插槽6是第三个 PCM 系统输入通道，可供麦克风专用。这个输入通道补充了真正的立体声输出，为扬声器应用提供了更精确的回音消除算法。ICH 支持插槽6输入的16位分辨率。

Input Slots 7-11: Reserved

Input frame slots 7-11 are reserved for future use and should be stuffed with zeros by the codec, per

the AC’97 specification.

Input Slot 12: I/O status

The status of the GPIOs configured as inputs are to be returned on this slot in every frame. The data

returned on the latest frame is accessible to software by reading the register at offset 54h/D4h in the

codec I/O space. Only the 16 MSBs are used to return GPI status. Bit 0 of this slot indicates the

GPI status. When a GPI changes state, this bit gets set for one frame by the codec. This bit can

cause an interrupt to the processor if enabled via the Global Control register.

Reads from 54h/D4h will not be transmitted across the link in slot 1 and 2. The data from the most

recent slot 12 is returned on reads from offset 54h/D4h.

输入插槽7-11: 保留的输入帧插槽7-11是为将来使用而保留的，应该由编解码器填充零，根据 AC’97规范。输入插槽12: I/O 状态配置为输入的 GPIO 的状态将在每帧中在这个插槽上返回。软件可以通过读取编解码器 I/O 空间中偏移54h/D4h 的寄存器来访问最新帧上返回的数据。只有16个 MSB 用于返回 GPI 状态。此插槽的第0位表示 GPI 状态。当 GPI 改变状态时，编解码器会为一帧设置这个位。如果通过全局控制寄存器启用此位，则可能导致处理器中断。从54h/D4h 读取的数据不会通过插槽1和2中的链路传输。在从偏移量54h/D4h 读取数据时，将返回最近插槽12中的数据。

5.17.4 Register Access

In the ICH implementation of the AC-link, up to two codecs can be connected to the SDOUT pin.

The following mechanism is used to address the primary and secondary codecs individually.

The primary device uses bit 19 of slot 1 as the direction bit to specify read or write. Bits [18:12] of

slot 1 are used for the register index. To access the primary codec, the valid bits [14:13] for slots

1 and 2 must be set in slot 0, as shown in Table 5-84. Slot 1 is used to transmit the register address

and slot 2 is used to transmit data.

The secondary codec registers are accessed using slots 1 and 2 as described above; however, the

slot valid bits for slots 1 and 2 are marked invalid in slot 0 and the codec ID bit 0 (bit 0 of slot 0) is

set to 1. This allows the secondary codec to monitor the slot valid bits of slots 1and 2, and bit 0 of

slot 0 to determine if the access is directed to the secondary codec. If the register access is targeted

to the secondary codec, slot 1 and 2 will contain the address and data for the register access. Since

slots 1 and 2 are marked invalid, the primary codec will ignore these accesses.

5.17.4注册访问在 ICH 实现的 AC-link 中，最多可以连接两个编解码器到 SDOUT 引脚。下面的机制用于分别寻址主编码解码器和辅助编码解码器。主设备使用插槽1的第19位作为指定读或写的方向位。位[18:12]的槽1用于寄存器索引。要访问主编解码器，插槽1和2的有效位[14:13]必须设置在插槽0中，如表5-84所示。插槽1用于传输寄存器地址，插槽2用于传输数据。如上所述，使用插槽1和2访问辅助编解码器寄存器; 然而，插槽1和2的插槽有效位在插槽0中被标记为无效，编解码器 ID 位0(插槽0的位0)被设置为1。这允许辅助编解码器监视插槽1和2的有效位，以及插槽0的0位，以确定访问是否定向到辅助编解码器。如果寄存器访问的目标是辅助编解码器，则插槽1和2将包含用于寄存器访问的地址和数据。由于插槽1和2被标记为无效，主编解码器将忽略这些访问。

Table 5-84. Output Tag Slot 0

表5-84. 输出标记槽0

When accessing the codec registers, only one I/O cycle can be pending across the AC-link at any

time. The ICH implements write posting on I/O writes across the AC-link (i.e., writes across the

link are indicated as complete before they are actually sent across the link). To prevent a second

I/O write from occurring before the first one is complete, software must monitor the CAS bit in the

Codec Access Semaphore register that indicates that a codec access is pending. Once the CAS bit is

cleared, another codec access (read or write) can go through. The exception to this being reads to

offset 54h/D4h (slot 12) that are returned immediately with the most recently received slot 12 data.

Writes to offset 54h and D4h (primary and secondary codecs) get transmitted across the AC-link in

slots 1 and 2 as a normal register access. Slot 12 is also updated immediately to reflect the data

being written.

The controller does not issue back to back reads. It must get a response to the first read before

issuing a second. In addition, codec reads and writes are only executed once across the link and are

not repeated.

当访问编解码器寄存器时，任何时候只有一个I/O 周期可以挂起在 AC 链路上。ICH 通过 AC-link 实现了对 I/O 写的写发送(例如，在实际通过链接发送之前，链接上的写被指示为完成)。为了防止在第一个 I/O 写完之前发生第二个 I/O 写，软件必须监视编解码器访问信号量寄存器中的 CAS 位，该寄存器指示一个编解码器访问挂起。一旦 CAS 位被清除，就可以通过另一个编解码器访问(读或写)。这种情况的例外是读取到与最近接收的第12个插槽数据一起立即返回的54h/D4h (插槽12)。写偏移54h 和 D4h (主编解码器和辅助编解码器)通过插槽1和2中的 AC 链路作为正常的寄存器访问进行传输。插槽12也会立即更新，以反映正在写入的数据。控制器不会发出返回读操作。它必须在发出第二个读操作之前获得对第一个读操作的响应。此外，编解码器的读和写只在链接上执行一次，不会重复执行。

5.18 AC-Link Low Power Mode

The AC-link signals can be placed in a low power mode. When the AC‘97 Powerdown Register

(26h) is programmed to the appropriate value, both BIT_CLK and SDIN will be brought to and

held at a logic low voltage level.

5.18 AC-Link 低功耗模式 AC-link 信号可以放置在低功耗模式下。当 AC’97降压寄存器(26h)被编程为适当的值时，BIT _ CLK 和 SDIN 都将被带到并保持在逻辑低电压水平。

Figure 5-20. AC-link Powerdown Timing

图5-20。交流链接断电时间

BIT_CLK and SDIN transition low immediately following a write to the Powerdown Register

(26h) with PR4. When the AC‘97 controller driver is at the point where it is ready to program the

AC-link into its low power mode, slots 1 and 2 are assumed to be the only valid stream in the audio

output frame.

The AC‘97 controller also drives AC_SYNC, and SDOUT low after programming AC‘97 to this

low power, halted mode

Once the codec has been instructed to halt BIT_CLK, a special wake up protocol must be used to

bring the AC-link to the active mode since normal output and input frames can not be

communicated in the absence of BIT_CLK. Once in a low power mode, the ICH provides three

methods for waking up the AC-link; external wake event, cold reset, and warm reset

Note: Before entering any low power mode where the link interface to the codec is expected to be

powered down while the rest of the system is awake, the software must set the "Shut Off" bit to 1 in

the control register.

BIT _ CLK 和 SDIN 转换在写入 PR4的 Powerdown Register (26h)后立即降低。当 AC’97控制器驱动程序在它准备编程的交流链接到它的低功率模式，槽1和2被认为是唯一有效的流在音频输出帧。AC’97控制器也驱动 AC _ SYNC，在编程 AC’97到这个低功耗、停止模式后，SDOUT 会降低。一旦编解码器被指示停止 BIT _ CLK，必须使用一个特殊的唤醒协议将 AC 链接带到有源模式，因为在没有 BIT _ CLK 的情况下，正常的输出和输入帧无法通信。一旦进入低功耗模式，ICH 提供了三种唤醒 AC 链路的方法: 外部唤醒事件、冷复位和温复位注意: 在进入任何低功耗模式之前，当系统的其余部分清醒时，编解码器的链路接口预计将被关闭，软件必须在控制寄存器中将“关闭”位设置为1。

5.18.1 External Wake Event

Codecs can signal the controller to wake the AC-link, and wake the system using SDIN.

5.18.1外部唤醒事件编解码器可以向控制器发出唤醒交流链路的信号，并使用 SDIN 唤醒系统。

Figure 5-21. SDIN Wake Signaling

图5-21。 SDIN 唤醒信号

The minimum SDIN wake up pulse width is 1 us. The rising edge of SDIN[0] or SDIN[1] causes

the ICH to sequence through an AC-link warm reset and set the AC97_STS bit to 1 in the

GPE0_STS register to wake the system. The primary codec must wait to sample AC_SYNC high

and low before restarting BIT_CLK as diagrammed in Figure 5-21. The codec that signaled the

wake event must keep its SDIN high until it has sampled AC_SYNC having gone high and then

low.

The AC-link protocol provides for a cold reset and a warm reset. The type of reset used depends on

the system’s current power down state. Unless a cold or register reset (a write to the Reset register

in the codec) is performed, wherein the AC‘97 codec registers are initialized to their default values,

registers are required to keep state during all power down modes.

Once powered down, activation of the AC-link via re-assertion of the AC_SYNC signal must not

occur for a minimum of 4 audio frame times following the frame in which the power down was

triggered. When AC-link powers up, it indicates readiness via the codec ready bit.

最小SDIN 唤醒脉冲宽度为1 us。SDIN [0]或 SDIN [1]的上升边缘导致 ICH 通过 AC 链路温复位进行排序，并在 GPE0 _ STS 寄存器中将 AC97 _ STS 位设置为1以唤醒系统。在重新启动 BIT _ CLK (如图5-21所示)之前，主编解码器必须等待采样 AC _ SYNC 的高和低。发出唤醒事件信号的编解码器必须保持其 SDIN 高，直到它对 AC _ SYNC 进行了先高后低的采样。交流链路协议提供冷复位和热复位。所使用的复位类型取决于系统当前的断电状态。除非执行冷重置或寄存器重置(向编解码器中的重置寄存器写入) ，其中 AC‘97编解码器寄存器被初始化为它们的默认值，寄存器在所有停电模式期间都需要保持状态。一旦断电，通过重新断言 AC _ SYNC 信号的 AC 链路的激活必须不发生在至少4个音频帧次之后的帧中断电被触发。当交流链路通电时，它通过编解码器就绪位指示准备就绪。

5.18.2 AC‘97 Cold Reset

A cold reset is achieved by asserting AC_RST# for 1 us. By driving AC_RST# low, BIT_CLK, and

SDOUT will be activated and all codec registers will be initialized to their default power on reset

values. AC_RST# is an asynchronous AC‘97 input to the codec.

5.18.3 AC‘97 Warm Reset

A warm reset re-activates the AC-link without altering the current codec register values. A warm

reset is signaled by driving AC_SYNC high for a minimum of 1 us in the absence of BIT_CLK.

Within normal frames, AC_SYNC is a synchronous AC‘97 input to the codec. However, in the

absence of BIT_CLK, AC_SYNC is treated as an asynchronous input to the codec used in the

generation of a warm reset.

The codec must not respond with the activation of BIT_CLK until AC_SYNC has been sampled

low again by the codec. This prevents the false detection of a new frame.

Note: On receipt of wake up signalling from the codec, the digital controller issues an interrupt, if

enabled. Software then has to issue a warm or cold reset to the codec by setting the appropriate bit

in the Global Control Register.

5.18.2 AC’97冷复位冷复位是通过断言 AC _ RST # 为1 us 来实现的。通过驱动 AC _ RST # low，BIT _ CLK 和 SDOUT 将被激活，所有编解码寄存器将在重置值上初始化为它们的默认功率。AC _ RST # 是编解码器的异步 AC‘97输入。5.18.3 AC’97暖复位暖复位重新激活 AC 链路而不改变当前编解码器寄存器值。在没有 BIT _ CLK 的情况下，通过驱动 AC _ SYNC 高至少1 us 来发出温复位信号。在正常帧中，AC _ SYNC 是编解码器的同步 AC‘97输入。但是，在没有 BIT _ CLK 的情况下，AC _ SYNC 被视为用于生成热复位的编解码器的异步输入。编解码器必须在 AC _ SYNC 被编解码器再次低采样之后才能响应激活 BIT _ CLK。这可以防止对新帧的错误检测。注意: 在接收到来自编解码器的唤醒信号时，如果启用，数字控制器将发出一个中断。然后，软件必须通过在全局控制寄存器中设置适当的位来发出一个暖的或冷的重置到编解码器。

5.18.4 System Reset

Table 5-85 indicates the states of the link during various system reset and sleep conditions.

5.18.4系统重置表5-85显示了在各种系统重置和睡眠条件下链路的状态。

Table 5-85. AC-link state during PCIRST#

表5-85. PCIRST # 期间的交流链路状态

NOTE:

1. ICH core well outputs are used as strapping options for the ICH sampled during system reset. These signals

may have weak pullups/pulldowns on them. The ICH outputs will be driven to the appropriate level prior to

AC_RST# being deasserted, preventing a codec from entering test mode. Straps are tied to the core well to

prevent leakage during a suspend state.

2. The pull-down resistors on these signals are only enabled when the AC-Link Shut Off bit in the AC’97 Global

Control Register is set to 1. All other times, the pull-down resistor is disabled.

3. AC_RST# is held low during S3-S5. It cannot be programmed high during a suspend state.

4. SDIN[1:0] are driven low by codecs during normal states. If the codec is powered in suspend states, it will

hold SDIN[1:0] low. However, if the codec is not present or not powered in suspend, external pull-downs are

required.

The transition of AC_RST# to the deasserted state only occurs under driver control. In the S1 sleep

state, the state of the AC_RST# signal is controlled by the AC’97 Cold Reset# bit (bit 1) in the

Global Control register. AC_RST# is asserted (low) by the ICH under the following conditions:

• RSMRST# (system reset, including the a reset of the resume well and PCIRST#)

• Mechanical power up (causes PCIRST#)

• Write to CF9h hard reset (causes PCIRST#)

• Transition to S3/S4/S5 sleep states (causes PCIRST#)

• Write to AC’97 Cold Reset# bit in the Global Control Register.

Hardware never deasserts AC_RST# (i.e., never deasserts the Cold Reset# bit) automatically. Only

software can deassert the Cold Reset# bit and, hence, the AC_RST# signal. This bit, while it

resides in the core well, remains cleared upon return from S3/S4/S5 sleep states. The AC_RST#

pin remains actively driven from the resume well as indicated.

注: 1。在系统复位过程中，ICH 核心井输出被用作 ICH 采样的捆绑选项。这些信号可能有微弱的上拉/下拉。ICH 输出将在 AC _ RST # 断言之前被驱动到适当的级别，从而阻止编解码器进入测试模式。皮带绑在芯井上，以防止在悬浮状态下发生泄漏。2.只有当 AC’97全局控制寄存器中的 AC-Link 关闭位设置为1时，这些信号上的下拉电阻才能启用。所有其他时候，下拉电阻被禁用。3.AC _ RST # 在 S3-S5期间保持低位。在挂起状态期间不能将其编程为高级。4.SDIN [1:0]在正常状态下由编解码器驱动。如果编解码器在挂起状态下运行，它将保持 SDIN [1:0]低。但是，如果编解码器不存在或在暂停中没有供电，则需要外部下拉。AC _ RST # 到断言状态的转换只发生在驱动程序控制下。在 S1睡眠状态下，AC _ RST # 信号的状态由全局控制寄存器中的 AC’97 Cold Reset # bit (bit 1)控制。ICH 在以下条件下断言 AC _ RST # (低) : • RSMRST # (系统重置，包括恢复良好的重置和 PCIRST #)•机械电源启动(导致 PCIRST #)•写入 CF9h 硬重置(导致 PCIRST #)•过渡到 S3/S4/S5睡眠状态(导致 PCIRST #)•写入全局控制寄存器中的 AC’97 Cold Reset # 位。硬件从不自动去断言 AC _ RST # (即，从不去断言 Cold Reset # 位)。只有软件可以去断言 Cold Reset # 位，因此也就是 AC _ RST # 信号。这个位，虽然它驻留在核心以及，仍然清除从 S3/S4/S5睡眠状态返回。AC _ RST # 引脚仍然主动地从简历驱动，如指示的那样。