L.4 ESDA/JEDEC JWIP-002-2021: Summary by Section

All length/width/height measurements – changed to metric only.

ESDA/JEDEC JTR002-01 – the term “see ESDA/JEDEC JTR002-01 - User Guide” was added as informational text in sections where more detail on a condition is provided in the new user guide.

FOREWORD – Foreword was updated to include the following:

New information includes a procedure to determine multiple level CDM withstand thresholds for subsets of device pins and a more accurate definition of verification module physical characteristics and capacitance measurement/use of modules. A companion technical report document, ESDA/JEDEC JTR002-01, has also been released to act as a “user guide” for this CDM test standard.

3.0 Definitions – Definitions for APL, supply pin, and no-connect pin were added.

5.1.3 Field Plate Dielectric – changed units to metric only; tolerance ± symbol removed from units.

6.9 Procedure for Evaluating Full CDM Tester Charging of a Device – Notes for charge time (delay) were added to this section, and the charge time terms were used in place of delay in this section.

7.1.3 and 7.1.4 – Existing Section 7.1.3 added header Tester Cleaning, and a new subsection 7.1.4 - Device Cleaning was added.

7.3.4 Field-Induced Charging Method – Clarified dual discharge procedure (with reference to informative Annex H) that stressing no-connect pins with this procedure will not charge them to the opposite polarity by the first discharge.

7.3.5 Allowance for Reduced Testing on Large Supply Pin Groups – New subsection describing allowance (and conditions for allowance) for stressing as few as ten pins of a supply pin group having greater than ten pins.

7.4.2 CDM Reporting Guidelines – Added reference to new Annex D for reporting multiple level thresholds.

Annexes

Annex A – Changes were made to the physical dimensions/tolerances of the small and large verification modules and the capacitance values/tolerances. Added Figure 3, which shows the verification module flatness. All subsequent figures in the document were renumbered sequentially upward.

Annex B – Changes were made to the capacitance measurement procedure of the verification modules, including a requirement that the side with the highest capacitance is used as the measurement side.

Annex D – A new normative annex was created to report withstand thresholds for multiple withstand thresholds of devices.

Subsequent annexes were renumbered accordingly.

Annex E – Updated Annex E to reduce historical content.

Annex G – Corrected NOTE at end of Section G.3 to account for measurement value of 1-ohm discharge resistor to calculate actual Ip.

Annex I – Updated existing flowcharts correcting waveform parameter symbols. Corrected Tables 6 and 7 reference to Ip1 changing to Ip.
Annex K – New annex added as a bibliography. Annex K becomes Annex L (revision history).

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