《CSAPP》（第3版）答案（第四章）
2024-06-27 16:08:04
《CSAPP》（第3版）答案（第四章）
P45
- A
不。if REG is %rsp, we push %rsp-8 instead of %rsp into stack如果REG是%rsp，那么入栈的是%rsp-8而不是%rsp。 - B
movq REG, -8(%rsp)
subq $8, %rsp
P46
- A
不是。如果REG是%rsp，movq (%rsp), REG将右边的值弹出到%esp中， 但是addq $8, %rsp改变了它的值 - B
addq $8, %rsp
movq 8(%rsp), REG
P47
- A
#include <stdio.h>
void bubble_ptr(long* data,long count){long *i,*last;for (last = data+count-1;last>data;last--){for (i=data;i<last;i++){if(*(i+1)<*i){long t = *(i+1);*(i+1) = *i;*i = t;}}}
}
int main(){long ass[4] = {1,8,4,0};bubble_ptr(ass,4);for(int i=0;i<4;i++)printf("%d ",ass[i]);
}- B
Sorry.
.pos 0irmovq stack, %rspcall mainhalt# Array of 4 elements
.align 8
data:.quad 0x0000000000000004.quad 0x0000000000000003.quad 0x0000000000000002
data_end:.quad 0x0000000000000001
main:irmovq data,%rdiirmovq data_end,%rsicall ysBubblePret
# long ys_bubble_p(long *data, long *end)
# data in %rdi, end in %rsi
ysBubbleP:jmp L2
L4:mrmovq 8(%rax), %r9mrmovq (%rax), %r10rrmovq %r9, %r8subq %r10, %r8jge L3rmmovq %r10, 8(%rax)rmmovq %r9, (%rax)
L3:irmovq $8, %r8addq %r8, %raxjmp L5
L6:rrmovq %rdi, %rax
L5:rrmovq %rsi, %r8subq %rax, %r8jg L4irmovq $8, %r8subq %r8, %rsi
L2:rrmovq %rsi, %r8subq %rdi, %r8jg L6ret
.pos 0x200
stack:
P48
Sorry.
.pos 0irmovq stack, %rspcall mainhalt
# Array of 4 elements
.align 8
data:.quad 0x0000000000000004.quad 0x0000000000000003.quad 0x0000000000000002
data_end:.quad 0x0000000000000001
main:irmovq data,%rdiirmovq data_end,%rsicall ysBubblePret
# long ys_bubble_p(long *data, long *end)
# data in %rdi, end in %rsi
ysBubbleP:jmp L2
L4:mrmovq 8(%rax), %r9mrmovq (%rax), %r10rrmovq %r9, %r8subq %r10, %r8
##############################################################
# begin differences
##############################################################cmovl %r9, %r11cmovl %r10, %r9cmovl %r11, %r10rmmovq %r9, 8(%rax)rmmovq %r10, (%rax)
##############################################################
# end
##############################################################irmovq $8, %r8addq %r8, %raxjmp L5
L6:rrmovq %rdi, %rax
L5:rrmovq %rsi, %r8subq %rax, %r8jg L4irmovq $8, %r8subq %r8, %rsi
L2:rrmovq %rsi, %r8subq %rdi, %r8jg L6ret
.pos 0x200
stack:
P49
注意，三个xorxorxor等价于一次交换，即：
x=x^y;
y=x^y;
x=x^y;所以：
.pos 0irmovq stack, %rspcall mainhalt# Array of 4 elements
.align 8
data:.quad 0x0000000000000004.quad 0x0000000000000003.quad 0x0000000000000002
data_end:.quad 0x0000000000000001main:irmovq data,%rdiirmovq data_end,%rsicall ysBubblePret
# long ys_bubble_p(long *data, long *end)
# data in %rdi, end in %rsi
ysBubbleP:jmp L2
L4:mrmovq 8(%rax), %r9mrmovq (%rax), %r10
############################################
# begin differences
############################################rrmovq %r9, %r8rrmovq %r10, %r11xorq %r9, %r10subq %r11, %r8cmovge %r11, %r9xorq %r10, %r9xorq %r9, %r10rmmovq %r9, 8(%rax)rmmovq %r10, (%rax)
############################################
# end
############################################irmovq $8, %r8addq %r8, %raxjmp L5
L6:rrmovq %rdi, %rax
L5:rrmovq %rsi, %r8subq %rax, %r8jg L4irmovq $8, %r8subq %r8, %rsi
L2:rrmovq %rsi, %r8subq %rdi, %r8jg L6ret
.pos 0x200
stack:
P50
.pos 0irmovq stack, %rspcall mainhalt# Array of 4 elements
.align 8
array:.quad 0x0000000000000000.quad 0x0000000000000000.quad 0x0000000000000000.quad 0x0000000000000000main:# test number 1, -1, 3, 5irmovq array, %r10irmovq $1,%rdicall switchvrmmovq %rax, (%r10)irmovq $-1,%rdicall switchvrmmovq %rax, 8(%r10)irmovq $3,%rdicall switchvrmmovq %rax, 16(%r10)irmovq $5,%rdicall switchvrmmovq %rax, 24(%r10)ret
table:.quad LD # default branch.quad L0 # idx == 0.quad L1 # idx == 1.quad L2 # idx == 2.quad L3 # idx == 3.quad L4 # idx == 4.quad L5 # idx == 5
# long switchv(long idx)
# idx in %rdi
switchv:# contant numberirmovq $8, %r8irmovq $0, %r10irmovq $1, %r11irmovq $0, %raxirmovq table, %rcx # table addressrrmovq %rdi, %rdxsubq %r8, %rdxjg def # idx > 5subq %r10, %rdijl def # idx < 0
mul: # calculate 8 * %rdisubq %r10, %rdije addraddq %r8, %rcxsubq %r11, %rdijmp mul
addr: # jump using table addressaddq %r8, %rcxmrmovq (%rcx), %rdipushq %rdiret
def: # default branchirmovq table, %rcxmrmovq (%rcx), %rdipushq %rdiret
L0:irmovq $0xaaa, %raxret
L1:jmp LD
L2:jmp L5
L3:irmovq $0xccc, %raxret
L4:jmp LD
L5:irmovq $0xbbb, %raxret
LD:irmovq $0xddd, %raxret
.pos 0x200
stack:
P51
| phase | iaddq V,rB |
|---|---|
| Fetch | icode:ifun = M1[PC]; rA:rB = M1[PC+1]; valC = M8[PC+2]; valP = PC + 10; |
| Decode | valB = R[rB] |
| Execute | valE = valB + valC; set CC |
| Memory | - |
| Writeback | R[rB] = valE |
| PC | PC = valP |
P52
#/* $begin seq-all-hcl */
####################################################################
# HCL Description of Control for Single Cycle Y86-64 Processor SEQ #
# Copyright (C) Randal E. Bryant, David R. O'Hallaron, 2010 #
###################################################################### Your task is to implement the iaddq instruction
## The file contains a declaration of the icodes
## for iaddq (IIADDQ)
## Your job is to add the rest of the logic to make it work####################################################################
# C Include's. Don't alter these #
####################################################################quote '#include <stdio.h>'
quote '#include "isa.h"'
quote '#include "sim.h"'
quote 'int sim_main(int argc, char *argv[]);'
quote 'word_t gen_pc(){return 0;}'
quote 'int main(int argc, char *argv[])'
quote ' {plusmode=0;return sim_main(argc,argv);}'####################################################################
# Declarations. Do not change/remove/delete any of these #
######################################################################### Symbolic representation of Y86-64 Instruction Codes #############
wordsig INOP 'I_NOP'
wordsig IHALT 'I_HALT'
wordsig IRRMOVQ 'I_RRMOVQ'
wordsig IIRMOVQ 'I_IRMOVQ'
wordsig IRMMOVQ 'I_RMMOVQ'
wordsig IMRMOVQ 'I_MRMOVQ'
wordsig IOPQ 'I_ALU'
wordsig IJXX 'I_JMP'
wordsig ICALL 'I_CALL'
wordsig IRET 'I_RET'
wordsig IPUSHQ 'I_PUSHQ'
wordsig IPOPQ 'I_POPQ'# Instruction code for iaddq instruction
wordsig IIADDQ 'I_IADDQ'##### Symbolic represenations of Y86-64 function codes #####
wordsig FNONE 'F_NONE' # Default function code##### Symbolic representation of Y86-64 Registers referenced explicitly #####
wordsig RRSP 'REG_RSP' # Stack Pointer
wordsig RNONE 'REG_NONE' # Special value indicating "no register"##### ALU Functions referenced explicitly #####
wordsig ALUADD 'A_ADD' # ALU should add its arguments##### Possible instruction status values #####
wordsig SAOK 'STAT_AOK' # Normal execution
wordsig SADR 'STAT_ADR' # Invalid memory address
wordsig SINS 'STAT_INS' # Invalid instruction
wordsig SHLT 'STAT_HLT' # Halt instruction encountered##### Signals that can be referenced by control logic ######################### Fetch stage inputs #####
wordsig pc 'pc' # Program counter
##### Fetch stage computations #####
wordsig imem_icode 'imem_icode' # icode field from instruction memory
wordsig imem_ifun 'imem_ifun' # ifun field from instruction memory
wordsig icode 'icode' # Instruction control code
wordsig ifun 'ifun' # Instruction function
wordsig rA 'ra' # rA field from instruction
wordsig rB 'rb' # rB field from instruction
wordsig valC 'valc' # Constant from instruction
wordsig valP 'valp' # Address of following instruction
boolsig imem_error 'imem_error' # Error signal from instruction memory
boolsig instr_valid 'instr_valid' # Is fetched instruction valid?##### Decode stage computations #####
wordsig valA 'vala' # Value from register A port
wordsig valB 'valb' # Value from register B port##### Execute stage computations #####
wordsig valE 'vale' # Value computed by ALU
boolsig Cnd 'cond' # Branch test##### Memory stage computations #####
wordsig valM 'valm' # Value read from memory
boolsig dmem_error 'dmem_error' # Error signal from data memory####################################################################
# Control Signal Definitions. #
#################################################################################### Fetch Stage #################################### Determine instruction code
word icode = [imem_error: INOP;1: imem_icode; # Default: get from instruction memory
];# Determine instruction function
word ifun = [imem_error: FNONE;1: imem_ifun; # Default: get from instruction memory
];bool instr_valid = icode in{ INOP, IHALT, IRRMOVQ, IIRMOVQ, IRMMOVQ, IMRMOVQ,IOPQ, IJXX, ICALL, IRET, IPUSHQ, IPOPQ, IIADDQ };# Does fetched instruction require a regid byte?
bool need_regids =icode in { IRRMOVQ, IOPQ, IPUSHQ, IPOPQ, IIRMOVQ, IRMMOVQ, IMRMOVQ, IIADDQ };# Does fetched instruction require a constant word?
bool need_valC =icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ, IJXX, ICALL, IIADDQ };################ Decode Stage ##################################### What register should be used as the A source?
word srcA = [icode in { IRRMOVQ, IRMMOVQ, IOPQ, IPUSHQ } : rA;icode in { IPOPQ, IRET } : RRSP;1 : RNONE; # Don't need register
];## What register should be used as the B source?
word srcB = [icode in { IOPQ, IRMMOVQ, IMRMOVQ, IIADDQ } : rB;icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;1 : RNONE; # Don't need register
];## What register should be used as the E destination?
word dstE = [icode in { IRRMOVQ } && Cnd : rB;icode in { IIRMOVQ, IOPQ, IIADDQ } : rB;icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;1 : RNONE; # Don't write any register
];## What register should be used as the M destination?
word dstM = [icode in { IMRMOVQ, IPOPQ } : rA;1 : RNONE; # Don't write any register
];################ Execute Stage ##################################### Select input A to ALUword aluA = [icode in { IRRMOVQ, IOPQ } : valA;icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ, IIADDQ } : valC;icode in { ICALL, IPUSHQ } : -8;icode in { IRET, IPOPQ } : 8;# Other instructions don't need ALU
];## Select input B to ALUword aluB = [icode in { IRMMOVQ, IMRMOVQ, IOPQ, ICALL,IPUSHQ, IRET, IPOPQ, IIADDQ } : valB;icode in { IRRMOVQ, IIRMOVQ } : 0;# Other instructions don't need ALU
];## Set the ALU functionword alufun = [icode == IOPQ : ifun;1 : ALUADD;
];## Should the condition codes be updated?bool set_cc = icode in { IOPQ, IIADDQ };################ Memory Stage ##################################### Set read control signal
bool mem_read = icode in { IMRMOVQ, IPOPQ, IRET };
## Set write control signal
bool mem_write = icode in { IRMMOVQ, IPUSHQ, ICALL };
## Select memory address
word mem_addr = [icode in { IRMMOVQ, IPUSHQ, ICALL, IMRMOVQ } : valE;icode in { IPOPQ, IRET } : valA;# Other instructions don't need address
];
## Select memory input data
word mem_data = [# Value from registericode in { IRMMOVQ, IPUSHQ } : valA;# Return PCicode == ICALL : valP;# Default: Don't write anything
];
## Determine instruction status
word Stat = [imem_error || dmem_error : SADR;!instr_valid: SINS;icode == IHALT : SHLT;1 : SAOK;
];
################ Program Counter Update ############################
## What address should instruction be fetched at
word new_pc = [# Call. Use instruction constanticode == ICALL : valC;# Taken branch. Use instruction constanticode == IJXX && Cnd : valC;# Completion of RET instruction. Use value from stackicode == IRET : valM;# Default: Use incremented PC1 : valP;
];
#/* $end seq-all-hcl */P53
#/* $begin pipe-stall-hcl */
####################################################################
# HCL Description of Control for Pipelined Y86-64 Processor #
# Copyright (C) Randal E. Bryant, David R. O'Hallaron, 2014 #
####################################################################
## Your task is to make the pipeline work without using any forwarding
## The normal bypassing logic in the file is disabled.
## You can only change the pipeline control logic at the end of this file.
## The trick is to make the pipeline stall whenever there is a data hazard.
####################################################################
# C Include's. Don't alter these #
####################################################################
quote '#include <stdio.h>'
quote '#include "isa.h"'
quote '#include "pipeline.h"'
quote '#include "stages.h"'
quote '#include "sim.h"'
quote 'int sim_main(int argc, char *argv[]);'
quote 'int main(int argc, char *argv[]){return sim_main(argc,argv);}'
####################################################################
# Declarations. Do not change/remove/delete any of these #
####################################################################
##### Symbolic representation of Y86-64 Instruction Codes #############
wordsig INOP 'I_NOP'
wordsig IHALT 'I_HALT'
wordsig IRRMOVQ 'I_RRMOVQ'
wordsig IIRMOVQ 'I_IRMOVQ'
wordsig IRMMOVQ 'I_RMMOVQ'
wordsig IMRMOVQ 'I_MRMOVQ'
wordsig IOPQ 'I_ALU'
wordsig IJXX 'I_JMP'
wordsig ICALL 'I_CALL'
wordsig IRET 'I_RET'
wordsig IPUSHQ 'I_PUSHQ'
wordsig IPOPQ 'I_POPQ'
##### Symbolic represenations of Y86-64 function codes #####
wordsig FNONE 'F_NONE' # Default function code
##### Symbolic representation of Y86-64 Registers referenced #####
wordsig RRSP 'REG_RSP' # Stack Pointer
wordsig RNONE 'REG_NONE' # Special value indicating "no register"
##### ALU Functions referenced explicitly ##########################
wordsig ALUADD 'A_ADD' # ALU should add its arguments
##### Possible instruction status values #####
wordsig SBUB 'STAT_BUB' # Bubble in stage
wordsig SAOK 'STAT_AOK' # Normal execution
wordsig SADR 'STAT_ADR' # Invalid memory address
wordsig SINS 'STAT_INS' # Invalid instruction
wordsig SHLT 'STAT_HLT' # Halt instruction encountered
##### Signals that can be referenced by control logic ##############
##### Pipeline Register F ##########################################
wordsig F_predPC 'pc_curr->pc' # Predicted value of PC
##### Intermediate Values in Fetch Stage ###########################
wordsig imem_icode 'imem_icode' # icode field from instruction memory
wordsig imem_ifun 'imem_ifun' # ifun field from instruction memory
wordsig f_icode 'if_id_next->icode' # (Possibly modified) instruction code
wordsig f_ifun 'if_id_next->ifun' # Fetched instruction function
wordsig f_valC 'if_id_next->valc' # Constant data of fetched instruction
wordsig f_valP 'if_id_next->valp' # Address of following instruction
boolsig imem_error 'imem_error' # Error signal from instruction memory
boolsig instr_valid 'instr_valid' # Is fetched instruction valid?
##### Pipeline Register D ##########################################
wordsig D_icode 'if_id_curr->icode' # Instruction code
wordsig D_rA 'if_id_curr->ra' # rA field from instruction
wordsig D_rB 'if_id_curr->rb' # rB field from instruction
wordsig D_valP 'if_id_curr->valp' # Incremented PC
##### Intermediate Values in Decode Stage #########################
wordsig d_srcA 'id_ex_next->srca' # srcA from decoded instruction
wordsig d_srcB 'id_ex_next->srcb' # srcB from decoded instruction
wordsig d_rvalA 'd_regvala' # valA read from register file
wordsig d_rvalB 'd_regvalb' # valB read from register file
##### Pipeline Register E ##########################################
wordsig E_icode 'id_ex_curr->icode' # Instruction code
wordsig E_ifun 'id_ex_curr->ifun' # Instruction function
wordsig E_valC 'id_ex_curr->valc' # Constant data
wordsig E_srcA 'id_ex_curr->srca' # Source A register ID
wordsig E_valA 'id_ex_curr->vala' # Source A value
wordsig E_srcB 'id_ex_curr->srcb' # Source B register ID
wordsig E_valB 'id_ex_curr->valb' # Source B value
wordsig E_dstE 'id_ex_curr->deste' # Destination E register ID
wordsig E_dstM 'id_ex_curr->destm' # Destination M register ID
##### Intermediate Values in Execute Stage #########################
wordsig e_valE 'ex_mem_next->vale' # valE generated by ALU
boolsig e_Cnd 'ex_mem_next->takebranch' # Does condition hold?
wordsig e_dstE 'ex_mem_next->deste' # dstE (possibly modified to be RNONE)
##### Pipeline Register M #########################
wordsig M_stat 'ex_mem_curr->status' # Instruction status
wordsig M_icode 'ex_mem_curr->icode' # Instruction code
wordsig M_ifun 'ex_mem_curr->ifun' # Instruction function
wordsig M_valA 'ex_mem_curr->vala' # Source A value
wordsig M_dstE 'ex_mem_curr->deste' # Destination E register ID
wordsig M_valE 'ex_mem_curr->vale' # ALU E value
wordsig M_dstM 'ex_mem_curr->destm' # Destination M register ID
boolsig M_Cnd 'ex_mem_curr->takebranch' # Condition flag
boolsig dmem_error 'dmem_error' # Error signal from instruction memory
##### Intermediate Values in Memory Stage ##########################
wordsig m_valM 'mem_wb_next->valm' # valM generated by memory
wordsig m_stat 'mem_wb_next->status' # stat (possibly modified to be SADR)
##### Pipeline Register W ##########################################
wordsig W_stat 'mem_wb_curr->status' # Instruction status
wordsig W_icode 'mem_wb_curr->icode' # Instruction code
wordsig W_dstE 'mem_wb_curr->deste' # Destination E register ID
wordsig W_valE 'mem_wb_curr->vale' # ALU E value
wordsig W_dstM 'mem_wb_curr->destm' # Destination M register ID
wordsig W_valM 'mem_wb_curr->valm' # Memory M value
####################################################################
# Control Signal Definitions. #
####################################################################
################ Fetch Stage ###################################
## What address should instruction be fetched at
word f_pc = [# Mispredicted branch. Fetch at incremented PCM_icode == IJXX && !M_Cnd : M_valA;# Completion of RET instructionW_icode == IRET : W_valM;# Default: Use predicted value of PC1 : F_predPC;
];
## Determine icode of fetched instruction
word f_icode = [imem_error : INOP;1: imem_icode;
];
# Determine ifun
word f_ifun = [imem_error : FNONE;1: imem_ifun;
];
# Is instruction valid?
bool instr_valid = f_icode in { INOP, IHALT, IRRMOVQ, IIRMOVQ, IRMMOVQ, IMRMOVQ,IOPQ, IJXX, ICALL, IRET, IPUSHQ, IPOPQ };
# Determine status code for fetched instruction
word f_stat = [imem_error: SADR;!instr_valid : SINS;f_icode == IHALT : SHLT;1 : SAOK;
];
# Does fetched instruction require a regid byte?
bool need_regids =f_icode in { IRRMOVQ, IOPQ, IPUSHQ, IPOPQ, IIRMOVQ, IRMMOVQ, IMRMOVQ };
# Does fetched instruction require a constant word?
bool need_valC =f_icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ, IJXX, ICALL };
# Predict next value of PC
word f_predPC = [f_icode in { IJXX, ICALL } : f_valC;1 : f_valP;
];
################ Decode Stage ######################################
## What register should be used as the A source?
word d_srcA = [D_icode in { IRRMOVQ, IRMMOVQ, IOPQ, IPUSHQ } : D_rA;D_icode in { IPOPQ, IRET } : RRSP;1 : RNONE; # Don't need register
];
## What register should be used as the B source?
word d_srcB = [D_icode in { IOPQ, IRMMOVQ, IMRMOVQ } : D_rB;D_icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;1 : RNONE; # Don't need register
];
## What register should be used as the E destination?
word d_dstE = [D_icode in { IRRMOVQ, IIRMOVQ, IOPQ} : D_rB;D_icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;1 : RNONE; # Don't write any register
];
## What register should be used as the M destination?
word d_dstM = [D_icode in { IMRMOVQ, IPOPQ } : D_rA;1 : RNONE; # Don't write any register
];
## What should be the A value?
## DO NOT MODIFY THE FOLLOWING CODE.
## No forwarding. valA is either valP or value from register file
word d_valA = [D_icode in { ICALL, IJXX } : D_valP; # Use incremented PC1 : d_rvalA; # Use value read from register file
];
## No forwarding. valB is value from register file
word d_valB = d_rvalB;
################ Execute Stage #####################################
## Select input A to ALU
word aluA = [E_icode in { IRRMOVQ, IOPQ } : E_valA;E_icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ } : E_valC;E_icode in { ICALL, IPUSHQ } : -8;E_icode in { IRET, IPOPQ } : 8;# Other instructions don't need ALU
];
## Select input B to ALU
word aluB = [E_icode in { IRMMOVQ, IMRMOVQ, IOPQ, ICALL,IPUSHQ, IRET, IPOPQ } : E_valB;E_icode in { IRRMOVQ, IIRMOVQ } : 0;# Other instructions don't need ALU
];
## Set the ALU function
word alufun = [E_icode == IOPQ : E_ifun;1 : ALUADD;
];
## Should the condition codes be updated?
bool set_cc = E_icode == IOPQ &&# State changes only during normal operation!m_stat in { SADR, SINS, SHLT } && !W_stat in { SADR, SINS, SHLT };
## Generate valA in execute stage
word e_valA = E_valA; # Pass valA through stage
## Set dstE to RNONE in event of not-taken conditional move
word e_dstE = [E_icode == IRRMOVQ && !e_Cnd : RNONE;1 : E_dstE;
];
################ Memory Stage ######################################
## Select memory address
word mem_addr = [M_icode in { IRMMOVQ, IPUSHQ, ICALL, IMRMOVQ } : M_valE;M_icode in { IPOPQ, IRET } : M_valA;# Other instructions don't need address
];
## Set read control signal
bool mem_read = M_icode in { IMRMOVQ, IPOPQ, IRET };
## Set write control signal
bool mem_write = M_icode in { IRMMOVQ, IPUSHQ, ICALL };
#/* $begin pipe-m_stat-hcl */
## Update the status
word m_stat = [dmem_error : SADR;1 : M_stat;
];
#/* $end pipe-m_stat-hcl */
## Set E port register ID
word w_dstE = W_dstE;
## Set E port value
word w_valE = W_valE;
## Set M port register ID
word w_dstM = W_dstM;
## Set M port value
word w_valM = W_valM;
## Update processor status
word Stat = [W_stat == SBUB : SAOK;1 : W_stat;
];
################ Pipeline Register Control #########################
# situation: ret
# bool s_ret = IRET in { D_icode, E_icode, M_icode };
#
# situation: jxx error
# bool s_jxx_error = (E_icode == IJXX && !e_Cnd);
#
# situation: data_hazard
# bool s_data_hazard =
# (
# (
# d_srcA != RNONE &&
# d_srcA in { e_dstE, E_dstM, M_dstM, M_dstE, W_dstM, W_dstE }
# ) ||
# (
# d_srcB != RNONE &&
# d_srcB in { e_dstE, E_dstM, M_dstM, M_dstE, W_dstM, W_dstE }
# )
# )
# Should I stall or inject a bubble into Pipeline Register F?
# At most one of these can be true.
# bool F_stall = (s_ret || s_data_hazard) && !s_jxx_error;
bool F_stall = ((IRET in { D_icode, E_icode, M_icode }) ||((d_srcA != RNONE &&d_srcA in { e_dstE, E_dstM, M_dstM, M_dstE, W_dstM, W_dstE }) ||(d_srcB != RNONE &&d_srcB in { e_dstE, E_dstM, M_dstM, M_dstE, W_dstM, W_dstE }))) &&!(E_icode == IJXX && !e_Cnd);
bool F_bubble = 0;
# Should I stall or inject a bubble into Pipeline Register D?
# At most one of these can be true.
# bool D_stall = s_data_hazard && !s_jxx_error;
# bool D_bubble = s_jxx_error || (!s_data_hazard && s_ret)
bool D_stall = ((d_srcA != RNONE &&d_srcA in { e_dstE, E_dstM, M_dstM, M_dstE, W_dstM, W_dstE }) ||(d_srcB != RNONE &&d_srcB in { e_dstE, E_dstM, M_dstM, M_dstE, W_dstM, W_dstE })) &&!(E_icode == IJXX && !e_Cnd);
bool D_bubble =(E_icode == IJXX && !e_Cnd) ||(!((d_srcA != RNONE &&d_srcA in { e_dstE, E_dstM, M_dstM, M_dstE, W_dstM, W_dstE }) ||(d_srcB != RNONE &&d_srcB in { e_dstE, E_dstM, M_dstM, M_dstE, W_dstM, W_dstE })) &&(IRET in { D_icode, E_icode, M_icode }));
# Should I stall or inject a bubble into Pipeline Register E?
# At most one of these can be true.
# bool E_stall = 0;
# bool E_bubble = s_jxx_error || s_data_hazard
bool E_stall = 0;
bool E_bubble =(E_icode == IJXX && !e_Cnd) ||((d_srcA != RNONE &&d_srcA in { e_dstE, E_dstM, M_dstM, M_dstE, W_dstM, W_dstE }) ||(d_srcB != RNONE &&d_srcB in { e_dstE, E_dstM, M_dstM, M_dstE, W_dstM, W_dstE }));
# Should I stall or inject a bubble into Pipeline Register M?
# At most one of these can be true.
bool M_stall = 0;
# Start injecting bubbles as soon as exception passes through memory stage
bool M_bubble = m_stat in { SADR, SINS, SHLT } || W_stat in { SADR, SINS, SHLT };
# Should I stall or inject a bubble into Pipeline Register W?
bool W_stall = W_stat in { SADR, SINS, SHLT };
bool W_bubble = 0;
#/* $end pipe-stall-hcl */
P54
#/* $begin pipe-all-hcl */
####################################################################
# HCL Description of Control for Pipelined Y86-64 Processor #
# Copyright (C) Randal E. Bryant, David R. O'Hallaron, 2014 #
####################################################################
## Your task is to implement the iaddq instruction
## The file contains a declaration of the icodes
## for iaddq (IIADDQ)
## Your job is to add the rest of the logic to make it work
####################################################################
# C Include's. Don't alter these #
####################################################################
quote '#include <stdio.h>'
quote '#include "isa.h"'
quote '#include "pipeline.h"'
quote '#include "stages.h"'
quote '#include "sim.h"'
quote 'int sim_main(int argc, char *argv[]);'
quote 'int main(int argc, char *argv[]){return sim_main(argc,argv);}'
####################################################################
# Declarations. Do not change/remove/delete any of these #
####################################################################
##### Symbolic representation of Y86-64 Instruction Codes #############
wordsig INOP 'I_NOP'
wordsig IHALT 'I_HALT'
wordsig IRRMOVQ 'I_RRMOVQ'
wordsig IIRMOVQ 'I_IRMOVQ'
wordsig IRMMOVQ 'I_RMMOVQ'
wordsig IMRMOVQ 'I_MRMOVQ'
wordsig IOPQ 'I_ALU'
wordsig IJXX 'I_JMP'
wordsig ICALL 'I_CALL'
wordsig IRET 'I_RET'
wordsig IPUSHQ 'I_PUSHQ'
wordsig IPOPQ 'I_POPQ'
# Instruction code for iaddq instruction
wordsig IIADDQ 'I_IADDQ'
##### Symbolic represenations of Y86-64 function codes #####
wordsig FNONE 'F_NONE' # Default function code
##### Symbolic representation of Y86-64 Registers referenced #####
wordsig RRSP 'REG_RSP' # Stack Pointer
wordsig RNONE 'REG_NONE' # Special value indicating "no register"
##### ALU Functions referenced explicitly ##########################
wordsig ALUADD 'A_ADD' # ALU should add its arguments
##### Possible instruction status values #####
wordsig SBUB 'STAT_BUB' # Bubble in stage
wordsig SAOK 'STAT_AOK' # Normal execution
wordsig SADR 'STAT_ADR' # Invalid memory address
wordsig SINS 'STAT_INS' # Invalid instruction
wordsig SHLT 'STAT_HLT' # Halt instruction encountered
##### Signals that can be referenced by control logic ##############
##### Pipeline Register F ##########################################
wordsig F_predPC 'pc_curr->pc' # Predicted value of PC
##### Intermediate Values in Fetch Stage ###########################
wordsig imem_icode 'imem_icode' # icode field from instruction memory
wordsig imem_ifun 'imem_ifun' # ifun field from instruction memory
wordsig f_icode 'if_id_next->icode' # (Possibly modified) instruction code
wordsig f_ifun 'if_id_next->ifun' # Fetched instruction function
wordsig f_valC 'if_id_next->valc' # Constant data of fetched instruction
wordsig f_valP 'if_id_next->valp' # Address of following instruction
boolsig imem_error 'imem_error' # Error signal from instruction memory
boolsig instr_valid 'instr_valid' # Is fetched instruction valid?
##### Pipeline Register D ##########################################
wordsig D_icode 'if_id_curr->icode' # Instruction code
wordsig D_rA 'if_id_curr->ra' # rA field from instruction
wordsig D_rB 'if_id_curr->rb' # rB field from instruction
wordsig D_valP 'if_id_curr->valp' # Incremented PC
##### Intermediate Values in Decode Stage #########################
wordsig d_srcA 'id_ex_next->srca' # srcA from decoded instruction
wordsig d_srcB 'id_ex_next->srcb' # srcB from decoded instruction
wordsig d_rvalA 'd_regvala' # valA read from register file
wordsig d_rvalB 'd_regvalb' # valB read from register file
##### Pipeline Register E ##########################################
wordsig E_icode 'id_ex_curr->icode' # Instruction code
wordsig E_ifun 'id_ex_curr->ifun' # Instruction function
wordsig E_valC 'id_ex_curr->valc' # Constant data
wordsig E_srcA 'id_ex_curr->srca' # Source A register ID
wordsig E_valA 'id_ex_curr->vala' # Source A value
wordsig E_srcB 'id_ex_curr->srcb' # Source B register ID
wordsig E_valB 'id_ex_curr->valb' # Source B value
wordsig E_dstE 'id_ex_curr->deste' # Destination E register ID
wordsig E_dstM 'id_ex_curr->destm' # Destination M register ID
##### Intermediate Values in Execute Stage #########################
wordsig e_valE 'ex_mem_next->vale' # valE generated by ALU
boolsig e_Cnd 'ex_mem_next->takebranch' # Does condition hold?
wordsig e_dstE 'ex_mem_next->deste' # dstE (possibly modified to be RNONE)
##### Pipeline Register M #########################
wordsig M_stat 'ex_mem_curr->status' # Instruction status
wordsig M_icode 'ex_mem_curr->icode' # Instruction code
wordsig M_ifun 'ex_mem_curr->ifun' # Instruction function
wordsig M_valA 'ex_mem_curr->vala' # Source A value
wordsig M_dstE 'ex_mem_curr->deste' # Destination E register ID
wordsig M_valE 'ex_mem_curr->vale' # ALU E value
wordsig M_dstM 'ex_mem_curr->destm' # Destination M register ID
boolsig M_Cnd 'ex_mem_curr->takebranch' # Condition flag
boolsig dmem_error 'dmem_error' # Error signal from instruction memory
##### Intermediate Values in Memory Stage ##########################
wordsig m_valM 'mem_wb_next->valm' # valM generated by memory
wordsig m_stat 'mem_wb_next->status' # stat (possibly modified to be SADR)
##### Pipeline Register W ##########################################
wordsig W_stat 'mem_wb_curr->status' # Instruction status
wordsig W_icode 'mem_wb_curr->icode' # Instruction code
wordsig W_dstE 'mem_wb_curr->deste' # Destination E register ID
wordsig W_valE 'mem_wb_curr->vale' # ALU E value
wordsig W_dstM 'mem_wb_curr->destm' # Destination M register ID
wordsig W_valM 'mem_wb_curr->valm' # Memory M value
####################################################################
# Control Signal Definitions. #
####################################################################
################ Fetch Stage ###################################
## What address should instruction be fetched at
word f_pc = [# Mispredicted branch. Fetch at incremented PCM_icode == IJXX && !M_Cnd : M_valA;# Completion of RET instructionW_icode == IRET : W_valM;# Default: Use predicted value of PC1 : F_predPC;
];
## Determine icode of fetched instruction
word f_icode = [imem_error : INOP;1: imem_icode;
];
# Determine ifun
word f_ifun = [imem_error : FNONE;1: imem_ifun;
];
# Is instruction valid?
bool instr_valid = f_icode in { INOP, IHALT, IRRMOVQ, IIRMOVQ, IRMMOVQ, IMRMOVQ,IOPQ, IJXX, ICALL, IRET, IPUSHQ, IPOPQ, IIADDQ };
# Determine status code for fetched instruction
word f_stat = [imem_error: SADR;!instr_valid : SINS;f_icode == IHALT : SHLT;1 : SAOK;
];
# Does fetched instruction require a regid byte?
bool need_regids =f_icode in { IRRMOVQ, IOPQ, IPUSHQ, IPOPQ, IIRMOVQ, IRMMOVQ, IMRMOVQ, IIADDQ };
# Does fetched instruction require a constant word?
bool need_valC =f_icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ, IJXX, ICALL, IIADDQ };
# Predict next value of PC
word f_predPC = [f_icode in { IJXX, ICALL } : f_valC;1 : f_valP;
];
################ Decode Stage ######################################
## What register should be used as the A source?
word d_srcA = [D_icode in { IRRMOVQ, IRMMOVQ, IOPQ, IPUSHQ } : D_rA;D_icode in { IPOPQ, IRET } : RRSP;1 : RNONE; # Don't need register
];
## What register should be used as the B source?
word d_srcB = [D_icode in { IOPQ, IRMMOVQ, IMRMOVQ, IIADDQ } : D_rB;D_icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;1 : RNONE; # Don't need register
];
## What register should be used as the E destination?
word d_dstE = [D_icode in { IRRMOVQ, IIRMOVQ, IOPQ, IIADDQ } : D_rB;D_icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;1 : RNONE; # Don't write any register
];
## What register should be used as the M destination?
word d_dstM = [D_icode in { IMRMOVQ, IPOPQ } : D_rA;1 : RNONE; # Don't write any register
];
## What should be the A value?
## Forward into decode stage for valA
word d_valA = [D_icode in { ICALL, IJXX } : D_valP; # Use incremented PCd_srcA == e_dstE : e_valE; # Forward valE from executed_srcA == M_dstM : m_valM; # Forward valM from memoryd_srcA == M_dstE : M_valE; # Forward valE from memoryd_srcA == W_dstM : W_valM; # Forward valM from write backd_srcA == W_dstE : W_valE; # Forward valE from write back1 : d_rvalA; # Use value read from register file
];
word d_valB = [d_srcB == e_dstE : e_valE; # Forward valE from executed_srcB == M_dstM : m_valM; # Forward valM from memoryd_srcB == M_dstE : M_valE; # Forward valE from memoryd_srcB == W_dstM : W_valM; # Forward valM from write backd_srcB == W_dstE : W_valE; # Forward valE from write back1 : d_rvalB; # Use value read from register file
];
################ Execute Stage #####################################
## Select input A to ALU
word aluA = [E_icode in { IRRMOVQ, IOPQ } : E_valA;E_icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ, IIADDQ } : E_valC;E_icode in { ICALL, IPUSHQ } : -8;E_icode in { IRET, IPOPQ } : 8;# Other instructions don't need ALU
];
## Select input B to ALU
word aluB = [E_icode in { IRMMOVQ, IMRMOVQ, IOPQ, ICALL, IPUSHQ, IRET, IPOPQ, IIADDQ } : E_valB;E_icode in { IRRMOVQ, IIRMOVQ } : 0;# Other instructions don't need ALU
]
## Set the ALU function
word alufun = [E_icode == IOPQ : E_ifun;1 : ALUADD;
];
## Should the condition codes be updated?
bool set_cc = (E_icode == IOPQ || E_icode == IIADDQ) &&# State changes only during normal operation!m_stat in { SADR, SINS, SHLT } && !W_stat in { SADR, SINS, SHLT };
## Generate valA in execute stage
word e_valA = E_valA; # Pass valA through stage
## Set dstE to RNONE in event of not-taken conditional move
word e_dstE = [E_icode == IRRMOVQ && !e_Cnd : RNONE;1 : E_dstE;
];
################ Memory Stage ######################################
## Select memory address
word mem_addr = [M_icode in { IRMMOVQ, IPUSHQ, ICALL, IMRMOVQ } : M_valE;M_icode in { IPOPQ, IRET } : M_valA;# Other instructions don't need address
];
## Set read control signal
bool mem_read = M_icode in { IMRMOVQ, IPOPQ, IRET };
## Set write control signal
bool mem_write = M_icode in { IRMMOVQ, IPUSHQ, ICALL };
#/* $begin pipe-m_stat-hcl */
## Update the status
word m_stat = [dmem_error : SADR;1 : M_stat;
];
#/* $end pipe-m_stat-hcl */
## Set E port register ID
word w_dstE = W_dstE;
## Set E port value
word w_valE = W_valE;
## Set M port register ID
word w_dstM = W_dstM;
## Set M port value
word w_valM = W_valM;
## Update processor status
word Stat = [W_stat == SBUB : SAOK;1 : W_stat;
];
################ Pipeline Register Control #########################
# Should I stall or inject a bubble into Pipeline Register F?
# At most one of these can be true.
bool F_bubble = 0;
bool F_stall =# Conditions for a load/use hazardE_icode in { IMRMOVQ, IPOPQ } &&E_dstM in { d_srcA, d_srcB } ||# Stalling at fetch while ret passes through pipelineIRET in { D_icode, E_icode, M_icode };
# Should I stall or inject a bubble into Pipeline Register D?
# At most one of these can be true.
bool D_stall = # Conditions for a load/use hazardE_icode in { IMRMOVQ, IPOPQ } &&E_dstM in { d_srcA, d_srcB };
bool D_bubble =# Mispredicted branch(E_icode == IJXX && !e_Cnd) ||# Stalling at fetch while ret passes through pipeline# but not condition for a load/use hazard!(E_icode in { IMRMOVQ, IPOPQ } && E_dstM in { d_srcA, d_srcB }) &&IRET in { D_icode, E_icode, M_icode };
# Should I stall or inject a bubble into Pipeline Register E?
# At most one of these can be true.
bool E_stall = 0;
bool E_bubble =# Mispredicted branch(E_icode == IJXX && !e_Cnd) ||# Conditions for a load/use hazardE_icode in { IMRMOVQ, IPOPQ } &&E_dstM in { d_srcA, d_srcB};
# Should I stall or inject a bubble into Pipeline Register M?
# At most one of these can be true.
bool M_stall = 0;
# Start injecting bubbles as soon as exception passes through memory stage
bool M_bubble = m_stat in { SADR, SINS, SHLT } || W_stat in { SADR, SINS, SHLT };
# Should I stall or inject a bubble into Pipeline Register W?
bool W_stall = W_stat in { SADR, SINS, SHLT };
bool W_bubble = 0;
#/* $end pipe-all-hcl */
P55
#/* $begin pipe-all-hcl */
####################################################################
# HCL Description of Control for Pipelined Y86-64 Processor #
# Copyright (C) Randal E. Bryant, David R. O'Hallaron, 2014 #
####################################################################
## Your task is to modify the design so that conditional branches are
## predicted as being not-taken. The code here is nearly identical
## to that for the normal pipeline.
## Comments starting with keyword "BNT" have been added at places
## relevant to the exercise.
####################################################################
# C Include's. Don't alter these #
####################################################################
quote '#include <stdio.h>'
quote '#include "isa.h"'
quote '#include "pipeline.h"'
quote '#include "stages.h"'
quote '#include "sim.h"'
quote 'int sim_main(int argc, char *argv[]);'
quote 'int main(int argc, char *argv[]){return sim_main(argc,argv);}'
####################################################################
# Declarations. Do not change/remove/delete any of these #
####################################################################
##### Symbolic representation of Y86-64 Instruction Codes #############
wordsig INOP 'I_NOP'
wordsig IHALT 'I_HALT'
wordsig IRRMOVQ 'I_RRMOVQ'
wordsig IIRMOVQ 'I_IRMOVQ'
wordsig IRMMOVQ 'I_RMMOVQ'
wordsig IMRMOVQ 'I_MRMOVQ'
wordsig IOPQ 'I_ALU'
wordsig IJXX 'I_JMP'
wordsig ICALL 'I_CALL'
wordsig IRET 'I_RET'
wordsig IPUSHQ 'I_PUSHQ'
wordsig IPOPQ 'I_POPQ'
##### Symbolic represenations of Y86-64 function codes #####
wordsig FNONE 'F_NONE' # Default function code
##### Symbolic representation of Y86-64 Registers referenced #####
wordsig RRSP 'REG_RSP' # Stack Pointer
wordsig RNONE 'REG_NONE' # Special value indicating "no register"
##### ALU Functions referenced explicitly ##########################
wordsig ALUADD 'A_ADD' # ALU should add its arguments
## BNT: For modified branch prediction, need to distinguish
## conditional vs. unconditional branches
##### Jump conditions referenced explicitly
wordsig UNCOND 'C_YES' # Unconditional transfer
##### Possible instruction status values #####
wordsig SBUB 'STAT_BUB' # Bubble in stage
wordsig SAOK 'STAT_AOK' # Normal execution
wordsig SADR 'STAT_ADR' # Invalid memory address
wordsig SINS 'STAT_INS' # Invalid instruction
wordsig SHLT 'STAT_HLT' # Halt instruction encountered
##### Signals that can be referenced by control logic ##############
##### Pipeline Register F ##########################################
wordsig F_predPC 'pc_curr->pc' # Predicted value of PC
##### Intermediate Values in Fetch Stage ###########################
wordsig imem_icode 'imem_icode' # icode field from instruction memory
wordsig imem_ifun 'imem_ifun' # ifun field from instruction memory
wordsig f_icode 'if_id_next->icode' # (Possibly modified) instruction code
wordsig f_ifun 'if_id_next->ifun' # Fetched instruction function
wordsig f_valC 'if_id_next->valc' # Constant data of fetched instruction
wordsig f_valP 'if_id_next->valp' # Address of following instruction
boolsig imem_error 'imem_error' # Error signal from instruction memory
boolsig instr_valid 'instr_valid' # Is fetched instruction valid?
##### Pipeline Register D ##########################################
wordsig D_icode 'if_id_curr->icode' # Instruction code
wordsig D_rA 'if_id_curr->ra' # rA field from instruction
wordsig D_rB 'if_id_curr->rb' # rB field from instruction
wordsig D_valP 'if_id_curr->valp' # Incremented PC
##### Intermediate Values in Decode Stage #########################
wordsig d_srcA 'id_ex_next->srca' # srcA from decoded instruction
wordsig d_srcB 'id_ex_next->srcb' # srcB from decoded instruction
wordsig d_rvalA 'd_regvala' # valA read from register file
wordsig d_rvalB 'd_regvalb' # valB read from register file
##### Pipeline Register E ##########################################
wordsig E_icode 'id_ex_curr->icode' # Instruction code
wordsig E_ifun 'id_ex_curr->ifun' # Instruction function
wordsig E_valC 'id_ex_curr->valc' # Constant data
wordsig E_srcA 'id_ex_curr->srca' # Source A register ID
wordsig E_valA 'id_ex_curr->vala' # Source A value
wordsig E_srcB 'id_ex_curr->srcb' # Source B register ID
wordsig E_valB 'id_ex_curr->valb' # Source B value
wordsig E_dstE 'id_ex_curr->deste' # Destination E register ID
wordsig E_dstM 'id_ex_curr->destm' # Destination M register ID
##### Intermediate Values in Execute Stage #########################
wordsig e_valE 'ex_mem_next->vale' # valE generated by ALU
boolsig e_Cnd 'ex_mem_next->takebranch' # Does condition hold?
wordsig e_dstE 'ex_mem_next->deste' # dstE (possibly modified to be RNONE)
##### Pipeline Register M #########################
wordsig M_stat 'ex_mem_curr->status' # Instruction status
wordsig M_icode 'ex_mem_curr->icode' # Instruction code
wordsig M_ifun 'ex_mem_curr->ifun' # Instruction function
wordsig M_valA 'ex_mem_curr->vala' # Source A value
wordsig M_dstE 'ex_mem_curr->deste' # Destination E register ID
wordsig M_valE 'ex_mem_curr->vale' # ALU E value
wordsig M_dstM 'ex_mem_curr->destm' # Destination M register ID
boolsig M_Cnd 'ex_mem_curr->takebranch' # Condition flag
boolsig dmem_error 'dmem_error' # Error signal from instruction memory
##### Intermediate Values in Memory Stage ##########################
wordsig m_valM 'mem_wb_next->valm' # valM generated by memory
wordsig m_stat 'mem_wb_next->status' # stat (possibly modified to be SADR)
##### Pipeline Register W ##########################################
wordsig W_stat 'mem_wb_curr->status' # Instruction status
wordsig W_icode 'mem_wb_curr->icode' # Instruction code
wordsig W_dstE 'mem_wb_curr->deste' # Destination E register ID
wordsig W_valE 'mem_wb_curr->vale' # ALU E value
wordsig W_dstM 'mem_wb_curr->destm' # Destination M register ID
wordsig W_valM 'mem_wb_curr->valm' # Memory M value
####################################################################
# Control Signal Definitions. #
####################################################################
################ Fetch Stage ###################################
## What address should instruction be fetched at
word f_pc = [# Mispredicted branch. Fetch at incremented PCM_icode == IJXX && M_ifun != UNCOND && M_Cnd : M_valA;# Completion of RET instructionW_icode == IRET : W_valM;# Default: Use predicted value of PC1 : F_predPC;
];
## Determine icode of fetched instruction
word f_icode = [imem_error : INOP;1: imem_icode;
];
# Determine ifun
word f_ifun = [imem_error : FNONE;1: imem_ifun;
];
# Is instruction valid?
bool instr_valid = f_icode in { INOP, IHALT, IRRMOVQ, IIRMOVQ, IRMMOVQ, IMRMOVQ,IOPQ, IJXX, ICALL, IRET, IPUSHQ, IPOPQ };
# Determine status code for fetched instruction
word f_stat = [imem_error: SADR;!instr_valid : SINS;f_icode == IHALT : SHLT;1 : SAOK;
];
# Does fetched instruction require a regid byte?
bool need_regids =f_icode in { IRRMOVQ, IOPQ, IPUSHQ, IPOPQ, IIRMOVQ, IRMMOVQ, IMRMOVQ };
# Does fetched instruction require a constant word?
bool need_valC =f_icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ, IJXX, ICALL };
# Predict next value of PC
word f_predPC = [# BNT: This is where you'll change the branch prediction rulef_icode == IJXX && f_ifun != UNCOND : f_valP;f_icode in { IJXX, ICALL } : f_valC;1 : f_valP;
];
################ Decode Stage ######################################
## What register should be used as the A source?
word d_srcA = [D_icode in { IRRMOVQ, IRMMOVQ, IOPQ, IPUSHQ } : D_rA;D_icode in { IPOPQ, IRET } : RRSP;1 : RNONE; # Don't need register
];
## What register should be used as the B source?
word d_srcB = [D_icode in { IOPQ, IRMMOVQ, IMRMOVQ } : D_rB;D_icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;1 : RNONE; # Don't need register
];
## What register should be used as the E destination?
word d_dstE = [D_icode in { IRRMOVQ, IIRMOVQ, IOPQ} : D_rB;D_icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;1 : RNONE; # Don't write any register
];
## What register should be used as the M destination?
word d_dstM = [D_icode in { IMRMOVQ, IPOPQ } : D_rA;1 : RNONE; # Don't write any register
];
## What should be the A value?
## Forward into decode stage for valA
word d_valA = [D_icode in { ICALL, IJXX } : D_valP; # Use incremented PCd_srcA == e_dstE : e_valE; # Forward valE from executed_srcA == M_dstM : m_valM; # Forward valM from memoryd_srcA == M_dstE : M_valE; # Forward valE from memoryd_srcA == W_dstM : W_valM; # Forward valM from write backd_srcA == W_dstE : W_valE; # Forward valE from write back1 : d_rvalA; # Use value read from register file
];
word d_valB = [d_srcB == e_dstE : e_valE; # Forward valE from executed_srcB == M_dstM : m_valM; # Forward valM from memoryd_srcB == M_dstE : M_valE; # Forward valE from memoryd_srcB == W_dstM : W_valM; # Forward valM from write backd_srcB == W_dstE : W_valE; # Forward valE from write back1 : d_rvalB; # Use value read from register file
];
################ Execute Stage #####################################
# BNT: When some branches are predicted as not-taken, you need some
# way to get valC into pipeline register M, so that
# you can correct for a mispredicted branch.
## Select input A to ALU
word aluA = [E_icode in { IRRMOVQ, IOPQ } : E_valA;E_icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ } : E_valC;E_icode in { ICALL, IPUSHQ } : -8;E_icode in { IRET, IPOPQ } : 8;# Other instructions don't need ALU
];
## Select input B to ALU
word aluB = [E_icode in { IRMMOVQ, IMRMOVQ, IOPQ, ICALL, IPUSHQ, IRET, IPOPQ } : E_valB;E_icode in { IRRMOVQ, IIRMOVQ } : 0;# Other instructions don't need ALU
];
## Set the ALU function
word alufun = [E_icode == IOPQ : E_ifun;1 : ALUADD;
];
## Should the condition codes be updated?
bool set_cc = E_icode == IOPQ &&# State changes only during normal operation!m_stat in { SADR, SINS, SHLT } && !W_stat in { SADR, SINS, SHLT };
## Generate valA in execute stage
## pass branch address back by M_valA
word e_valA = [E_icode == IJXX && E_ifun != UNCOND : E_valC;1 : E_valA; # Pass valA through stage
];
## Set dstE to RNONE in event of not-taken conditional move
word e_dstE = [E_icode == IRRMOVQ && !e_Cnd : RNONE;1 : E_dstE;
];
################ Memory Stage ######################################
## Select memory address
word mem_addr = [M_icode in { IRMMOVQ, IPUSHQ, ICALL, IMRMOVQ } : M_valE;M_icode in { IPOPQ, IRET } : M_valA;# Other instructions don't need address
];
## Set read control signal
bool mem_read = M_icode in { IMRMOVQ, IPOPQ, IRET };
## Set write control signal
bool mem_write = M_icode in { IRMMOVQ, IPUSHQ, ICALL };
#/* $begin pipe-m_stat-hcl */
## Update the status
word m_stat = [dmem_error : SADR;1 : M_stat;
];
#/* $end pipe-m_stat-hcl */
## Set E port register ID
word w_dstE = W_dstE;
## Set E port value
word w_valE = W_valE;
## Set M port register ID
word w_dstM = W_dstM;
## Set M port value
word w_valM = W_valM;
## Update processor status
word Stat = [W_stat == SBUB : SAOK;1 : W_stat;
];
################ Pipeline Register Control #########################
# Should I stall or inject a bubble into Pipeline Register F?
# At most one of these can be true.
bool F_bubble = 0;
bool F_stall =# Conditions for a load/use hazardE_icode in { IMRMOVQ, IPOPQ } &&E_dstM in { d_srcA, d_srcB } ||# Stalling at fetch while ret passes through pipelineIRET in { D_icode, E_icode, M_icode };
# Should I stall or inject a bubble into Pipeline Register D?
# At most one of these can be true.
bool D_stall = # Conditions for a load/use hazardE_icode in { IMRMOVQ, IPOPQ } &&E_dstM in { d_srcA, d_srcB };
bool D_bubble =# Mispredicted branch(E_icode == IJXX && E_ifun != UNCOND && e_Cnd) ||# Stalling at fetch while ret passes through pipeline# but not condition for a load/use hazard!(E_icode in { IMRMOVQ, IPOPQ } && E_dstM in { d_srcA, d_srcB }) &&IRET in { D_icode, E_icode, M_icode };
# Should I stall or inject a bubble into Pipeline Register E?
# At most one of these can be true.
bool E_stall = 0;
bool E_bubble =# Mispredicted branch(E_icode == IJXX && E_ifun != UNCOND && e_Cnd) ||# Conditions for a load/use hazardE_icode in { IMRMOVQ, IPOPQ } &&E_dstM in { d_srcA, d_srcB};
# Should I stall or inject a bubble into Pipeline Register M?
# At most one of these can be true.
bool M_stall = 0;
# Start injecting bubbles as soon as exception passes through memory stage
bool M_bubble = m_stat in { SADR, SINS, SHLT } || W_stat in { SADR, SINS, SHLT };
# Should I stall or inject a bubble into Pipeline Register W?
bool W_stall = W_stat in { SADR, SINS, SHLT };
bool W_bubble = 0;
#/* $end pipe-all-hcl */
P56
#/* $begin pipe-all-hcl */
####################################################################
# HCL Description of Control for Pipelined Y86-64 Processor #
# Copyright (C) Randal E. Bryant, David R. O'Hallaron, 2014 #
####################################################################
## Your task is to modify the design so that conditional branches are
## predicted as being taken when backward and not-taken when forward
## The code here is nearly identical to that for the normal pipeline.
## Comments starting with keyword "BBTFNT" have been added at places
## relevant to the exercise.
####################################################################
# C Include's. Don't alter these #
####################################################################
quote '#include <stdio.h>'
quote '#include "isa.h"'
quote '#include "pipeline.h"'
quote '#include "stages.h"'
quote '#include "sim.h"'
quote 'int sim_main(int argc, char *argv[]);'
quote 'int main(int argc, char *argv[]){return sim_main(argc,argv);}'
####################################################################
# Declarations. Do not change/remove/delete any of these #
####################################################################
##### Symbolic representation of Y86-64 Instruction Codes #############
wordsig INOP 'I_NOP'
wordsig IHALT 'I_HALT'
wordsig IRRMOVQ 'I_RRMOVQ'
wordsig IIRMOVQ 'I_IRMOVQ'
wordsig IRMMOVQ 'I_RMMOVQ'
wordsig IMRMOVQ 'I_MRMOVQ'
wordsig IOPQ 'I_ALU'
wordsig IJXX 'I_JMP'
wordsig ICALL 'I_CALL'
wordsig IRET 'I_RET'
wordsig IPUSHQ 'I_PUSHQ'
wordsig IPOPQ 'I_POPQ'
##### Symbolic represenations of Y86-64 function codes #####
wordsig FNONE 'F_NONE' # Default function code
##### Symbolic representation of Y86-64 Registers referenced #####
wordsig RRSP 'REG_RSP' # Stack Pointer
wordsig RNONE 'REG_NONE' # Special value indicating "no register"
##### ALU Functions referenced explicitly ##########################
wordsig ALUADD 'A_ADD' # ALU should add its arguments
## BBTFNT: For modified branch prediction, need to distinguish
## conditional vs. unconditional branches
##### Jump conditions referenced explicitly
wordsig UNCOND 'C_YES' # Unconditional transfer
##### Possible instruction status values #####
wordsig SBUB 'STAT_BUB' # Bubble in stage
wordsig SAOK 'STAT_AOK' # Normal execution
wordsig SADR 'STAT_ADR' # Invalid memory address
wordsig SINS 'STAT_INS' # Invalid instruction
wordsig SHLT 'STAT_HLT' # Halt instruction encountered
##### Signals that can be referenced by control logic ##############
##### Pipeline Register F ##########################################
wordsig F_predPC 'pc_curr->pc' # Predicted value of PC
##### Intermediate Values in Fetch Stage ###########################
wordsig imem_icode 'imem_icode' # icode field from instruction memory
wordsig imem_ifun 'imem_ifun' # ifun field from instruction memory
wordsig f_icode 'if_id_next->icode' # (Possibly modified) instruction code
wordsig f_ifun 'if_id_next->ifun' # Fetched instruction function
wordsig f_valC 'if_id_next->valc' # Constant data of fetched instruction
wordsig f_valP 'if_id_next->valp' # Address of following instruction
boolsig imem_error 'imem_error' # Error signal from instruction memory
boolsig instr_valid 'instr_valid' # Is fetched instruction valid?
##### Pipeline Register D ##########################################
wordsig D_icode 'if_id_curr->icode' # Instruction code
wordsig D_rA 'if_id_curr->ra' # rA field from instruction
wordsig D_rB 'if_id_curr->rb' # rB field from instruction
wordsig D_valP 'if_id_curr->valp' # Incremented PC
##### Intermediate Values in Decode Stage #########################
wordsig d_srcA 'id_ex_next->srca' # srcA from decoded instruction
wordsig d_srcB 'id_ex_next->srcb' # srcB from decoded instruction
wordsig d_rvalA 'd_regvala' # valA read from register file
wordsig d_rvalB 'd_regvalb' # valB read from register file
##### Pipeline Register E ##########################################
wordsig E_icode 'id_ex_curr->icode' # Instruction code
wordsig E_ifun 'id_ex_curr->ifun' # Instruction function
wordsig E_valC 'id_ex_curr->valc' # Constant data
wordsig E_srcA 'id_ex_curr->srca' # Source A register ID
wordsig E_valA 'id_ex_curr->vala' # Source A value
wordsig E_srcB 'id_ex_curr->srcb' # Source B register ID
wordsig E_valB 'id_ex_curr->valb' # Source B value
wordsig E_dstE 'id_ex_curr->deste' # Destination E register ID
wordsig E_dstM 'id_ex_curr->destm' # Destination M register ID
##### Intermediate Values in Execute Stage #########################
wordsig e_valE 'ex_mem_next->vale' # valE generated by ALU
boolsig e_Cnd 'ex_mem_next->takebranch' # Does condition hold?
wordsig e_dstE 'ex_mem_next->deste' # dstE (possibly modified to be RNONE)
##### Pipeline Register M #########################
wordsig M_stat 'ex_mem_curr->status' # Instruction status
wordsig M_icode 'ex_mem_curr->icode' # Instruction code
wordsig M_ifun 'ex_mem_curr->ifun' # Instruction function
wordsig M_valA 'ex_mem_curr->vala' # Source A value
wordsig M_dstE 'ex_mem_curr->deste' # Destination E register ID
wordsig M_valE 'ex_mem_curr->vale' # ALU E value
wordsig M_dstM 'ex_mem_curr->destm' # Destination M register ID
boolsig M_Cnd 'ex_mem_curr->takebranch' # Condition flag
boolsig dmem_error 'dmem_error' # Error signal from instruction memory
##### Intermediate Values in Memory Stage ##########################
wordsig m_valM 'mem_wb_next->valm' # valM generated by memory
wordsig m_stat 'mem_wb_next->status' # stat (possibly modified to be SADR)
##### Pipeline Register W ##########################################
wordsig W_stat 'mem_wb_curr->status' # Instruction status
wordsig W_icode 'mem_wb_curr->icode' # Instruction code
wordsig W_dstE 'mem_wb_curr->deste' # Destination E register ID
wordsig W_valE 'mem_wb_curr->vale' # ALU E value
wordsig W_dstM 'mem_wb_curr->destm' # Destination M register ID
wordsig W_valM 'mem_wb_curr->valm' # Memory M value
####################################################################
# Control Signal Definitions. #
####################################################################
################ Fetch Stage ###################################
## What address should instruction be fetched at
word f_pc = [# Mispredicted branch. Fetch at incremented PC# backward taken errorM_icode == IJXX && M_ifun != UNCOND && M_valE < M_valA && !M_Cnd : M_valA;# forward not-taken errorM_icode == IJXX && M_ifun != UNCOND && M_valE >= M_valA && M_Cnd : M_valE;# Completion of RET instructionW_icode == IRET : W_valM;# Default: Use predicted value of PC1 : F_predPC;
];
## Determine icode of fetched instruction
word f_icode = [imem_error : INOP;1: imem_icode;
];
# Determine ifun
word f_ifun = [imem_error : FNONE;1: imem_ifun;
];
# Is instruction valid?
bool instr_valid = f_icode in { INOP, IHALT, IRRMOVQ, IIRMOVQ, IRMMOVQ, IMRMOVQ,IOPQ, IJXX, ICALL, IRET, IPUSHQ, IPOPQ };
# Determine status code for fetched instruction
word f_stat = [imem_error: SADR;!instr_valid : SINS;f_icode == IHALT : SHLT;1 : SAOK;
];
# Does fetched instruction require a regid byte?
bool need_regids =f_icode in { IRRMOVQ, IOPQ, IPUSHQ, IPOPQ, IIRMOVQ, IRMMOVQ, IMRMOVQ };
# Does fetched instruction require a constant word?
bool need_valC =f_icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ, IJXX, ICALL };
# Predict next value of PC
word f_predPC = [# BBTFNT: This is where you'll change the branch prediction rulef_icode == IJXX && f_ifun != UNCOND && f_valC < f_valP : f_valC;f_icode == IJXX && f_ifun != UNCOND && f_valC >= f_valP : f_valP;f_icode in { IJXX, ICALL } : f_valC;1 : f_valP;
];
################ Decode Stage ######################################
## What register should be used as the A source?
word d_srcA = [D_icode in { IRRMOVQ, IRMMOVQ, IOPQ, IPUSHQ } : D_rA;D_icode in { IPOPQ, IRET } : RRSP;1 : RNONE; # Don't need register
];
## What register should be used as the B source?
word d_srcB = [D_icode in { IOPQ, IRMMOVQ, IMRMOVQ } : D_rB;D_icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;1 : RNONE; # Don't need register
];
## What register should be used as the E destination?
word d_dstE = [D_icode in { IRRMOVQ, IIRMOVQ, IOPQ} : D_rB;D_icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;1 : RNONE; # Don't write any register
];
## What register should be used as the M destination?
word d_dstM = [D_icode in { IMRMOVQ, IPOPQ } : D_rA;1 : RNONE; # Don't write any register
];
## What should be the A value?
## Forward into decode stage for valA
word d_valA = [D_icode in { ICALL, IJXX } : D_valP; # Use incremented PCd_srcA == e_dstE : e_valE; # Forward valE from executed_srcA == M_dstM : m_valM; # Forward valM from memoryd_srcA == M_dstE : M_valE; # Forward valE from memoryd_srcA == W_dstM : W_valM; # Forward valM from write backd_srcA == W_dstE : W_valE; # Forward valE from write back1 : d_rvalA; # Use value read from register file
];
word d_valB = [d_srcB == e_dstE : e_valE; # Forward valE from executed_srcB == M_dstM : m_valM; # Forward valM from memoryd_srcB == M_dstE : M_valE; # Forward valE from memoryd_srcB == W_dstM : W_valM; # Forward valM from write backd_srcB == W_dstE : W_valE; # Forward valE from write back1 : d_rvalB; # Use value read from register file
];
################ Execute Stage #####################################
# BBTFNT: When some branches are predicted as not-taken, you need some
# way to get valC into pipeline register M, so that
# you can correct for a mispredicted branch.
## pass valC by M_valE, pass valP by M_valA
## Select input A to ALU
word aluA = [E_icode in { IRRMOVQ, IOPQ } : E_valA;E_icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ } : E_valC;E_icode in { ICALL, IPUSHQ } : -8;E_icode in { IRET, IPOPQ } : 8;E_icode in { IJXX } : E_valC;# Other instructions don't need ALU
];
## Select input B to ALU
word aluB = [E_icode in { IRMMOVQ, IMRMOVQ, IOPQ, ICALL, IPUSHQ, IRET, IPOPQ } : E_valB;E_icode in { IRRMOVQ, IIRMOVQ } : 0;E_icode in { IJXX } : 0;# Other instructions don't need ALU
];
## Set the ALU function
word alufun = [E_icode == IOPQ : E_ifun;1 : ALUADD;
];
## Should the condition codes be updated?
bool set_cc = E_icode == IOPQ &&# State changes only during normal operation!m_stat in { SADR, SINS, SHLT } && !W_stat in { SADR, SINS, SHLT };
## Generate valA in execute stage
word e_valA = E_valA; # Pass valA through stage
## Set dstE to RNONE in event of not-taken conditional move
word e_dstE = [E_icode == IRRMOVQ && !e_Cnd : RNONE;1 : E_dstE;
];
################ Memory Stage ######################################
## Select memory address
word mem_addr = [M_icode in { IRMMOVQ, IPUSHQ, ICALL, IMRMOVQ } : M_valE;M_icode in { IPOPQ, IRET } : M_valA;# Other instructions don't need address
];
## Set read control signal
bool mem_read = M_icode in { IMRMOVQ, IPOPQ, IRET };
## Set write control signal
bool mem_write = M_icode in { IRMMOVQ, IPUSHQ, ICALL };
#/* $begin pipe-m_stat-hcl */
## Update the status
word m_stat = [dmem_error : SADR;1 : M_stat;
];
#/* $end pipe-m_stat-hcl */
## Set E port register ID
word w_dstE = W_dstE;
## Set E port value
word w_valE = W_valE;
## Set M port register ID
word w_dstM = W_dstM;
## Set M port value
word w_valM = W_valM;
## Update processor status
word Stat = [W_stat == SBUB : SAOK;1 : W_stat;
];
################ Pipeline Register Control #########################
# Should I stall or inject a bubble into Pipeline Register F?
# At most one of these can be true.
bool F_bubble = 0;
bool F_stall =# Conditions for a load/use hazardE_icode in { IMRMOVQ, IPOPQ } &&E_dstM in { d_srcA, d_srcB } ||# Stalling at fetch while ret passes through pipelineIRET in { D_icode, E_icode, M_icode };
# Should I stall or inject a bubble into Pipeline Register D?
# At most one of these can be true.
bool D_stall = # Conditions for a load/use hazardE_icode in { IMRMOVQ, IPOPQ } &&E_dstM in { d_srcA, d_srcB };
bool D_bubble =# Mispredicted branch# backward taken error or forward not-taken error((E_icode == IJXX && E_ifun != UNCOND && E_valC < E_valA && !e_Cnd) ||(E_icode == IJXX && E_ifun != UNCOND && E_valC >= E_valA && e_Cnd)) ||# BBTFNT: This condition will change# Stalling at fetch while ret passes through pipeline# but not condition for a load/use hazard!(E_icode in { IMRMOVQ, IPOPQ } && E_dstM in { d_srcA, d_srcB }) &&IRET in { D_icode, E_icode, M_icode };
# Should I stall or inject a bubble into Pipeline Register E?
# At most one of these can be true.
bool E_stall = 0;
bool E_bubble =# Mispredicted branch# backward taken error or forward not-taken error((E_icode == IJXX && E_ifun != UNCOND && E_valC < E_valA && !e_Cnd) ||(E_icode == IJXX && E_ifun != UNCOND && E_valC >= E_valA && e_Cnd)) ||# BBTFNT: This condition will change# Conditions for a load/use hazardE_icode in { IMRMOVQ, IPOPQ } &&E_dstM in { d_srcA, d_srcB};
# Should I stall or inject a bubble into Pipeline Register M?
# At most one of these can be true.
bool M_stall = 0;
# Start injecting bubbles as soon as exception passes through memory stage
bool M_bubble = m_stat in { SADR, SINS, SHLT } || W_stat in { SADR, SINS, SHLT };
# Should I stall or inject a bubble into Pipeline Register W?
bool W_stall = W_stat in { SADR, SINS, SHLT };
bool W_bubble = 0;
#/* $end pipe-all-hcl */P57
- A
Sorry. It is beyond my range. - B
#/* $begin pipe-all-hcl */
####################################################################
# HCL Description of Control for Pipelined Y86-64 Processor #
# Copyright (C) Randal E. Bryant, David R. O'Hallaron, 2014 #
####################################################################
## Your task is to implement load-forwarding, where a value
## read from memory can be stored to memory by the immediately
## following instruction without stalling
## This requires modifying the definition of e_valA
## and relaxing the stall conditions. Relevant sections to change
## are shown in comments containing the keyword "LB"
####################################################################
# C Include's. Don't alter these #
####################################################################
quote '#include <stdio.h>'
quote '#include "isa.h"'
quote '#include "pipeline.h"'
quote '#include "stages.h"'
quote '#include "sim.h"'
quote 'int sim_main(int argc, char *argv[]);'
quote 'int main(int argc, char *argv[]){return sim_main(argc,argv);}'
####################################################################
# Declarations. Do not change/remove/delete any of these #
####################################################################
##### Symbolic representation of Y86-64 Instruction Codes #############
wordsig INOP 'I_NOP'
wordsig IHALT 'I_HALT'
wordsig IRRMOVQ 'I_RRMOVQ'
wordsig IIRMOVQ 'I_IRMOVQ'
wordsig IRMMOVQ 'I_RMMOVQ'
wordsig IMRMOVQ 'I_MRMOVQ'
wordsig IOPQ 'I_ALU'
wordsig IJXX 'I_JMP'
wordsig ICALL 'I_CALL'
wordsig IRET 'I_RET'
wordsig IPUSHQ 'I_PUSHQ'
wordsig IPOPQ 'I_POPQ'
##### Symbolic represenations of Y86-64 function codes #####
wordsig FNONE 'F_NONE' # Default function code
##### Symbolic representation of Y86-64 Registers referenced #####
wordsig RRSP 'REG_RSP' # Stack Pointer
wordsig RNONE 'REG_NONE' # Special value indicating "no register"
##### ALU Functions referenced explicitly ##########################
wordsig ALUADD 'A_ADD' # ALU should add its arguments
##### Possible instruction status values #####
wordsig SBUB 'STAT_BUB' # Bubble in stage
wordsig SAOK 'STAT_AOK' # Normal execution
wordsig SADR 'STAT_ADR' # Invalid memory address
wordsig SINS 'STAT_INS' # Invalid instruction
wordsig SHLT 'STAT_HLT' # Halt instruction encountered
##### Signals that can be referenced by control logic ##############
##### Pipeline Register F ##########################################
wordsig F_predPC 'pc_curr->pc' # Predicted value of PC
##### Intermediate Values in Fetch Stage ###########################
wordsig imem_icode 'imem_icode' # icode field from instruction memory
wordsig imem_ifun 'imem_ifun' # ifun field from instruction memory
wordsig f_icode 'if_id_next->icode' # (Possibly modified) instruction code
wordsig f_ifun 'if_id_next->ifun' # Fetched instruction function
wordsig f_valC 'if_id_next->valc' # Constant data of fetched instruction
wordsig f_valP 'if_id_next->valp' # Address of following instruction
boolsig imem_error 'imem_error' # Error signal from instruction memory
boolsig instr_valid 'instr_valid' # Is fetched instruction valid?
##### Pipeline Register D ##########################################
wordsig D_icode 'if_id_curr->icode' # Instruction code
wordsig D_rA 'if_id_curr->ra' # rA field from instruction
wordsig D_rB 'if_id_curr->rb' # rB field from instruction
wordsig D_valP 'if_id_curr->valp' # Incremented PC
##### Intermediate Values in Decode Stage #########################
wordsig d_srcA 'id_ex_next->srca' # srcA from decoded instruction
wordsig d_srcB 'id_ex_next->srcb' # srcB from decoded instruction
wordsig d_rvalA 'd_regvala' # valA read from register file
wordsig d_rvalB 'd_regvalb' # valB read from register file
##### Pipeline Register E ##########################################
wordsig E_icode 'id_ex_curr->icode' # Instruction code
wordsig E_ifun 'id_ex_curr->ifun' # Instruction function
wordsig E_valC 'id_ex_curr->valc' # Constant data
wordsig E_srcA 'id_ex_curr->srca' # Source A register ID
wordsig E_valA 'id_ex_curr->vala' # Source A value
wordsig E_srcB 'id_ex_curr->srcb' # Source B register ID
wordsig E_valB 'id_ex_curr->valb' # Source B value
wordsig E_dstE 'id_ex_curr->deste' # Destination E register ID
wordsig E_dstM 'id_ex_curr->destm' # Destination M register ID
##### Intermediate Values in Execute Stage #########################
wordsig e_valE 'ex_mem_next->vale' # valE generated by ALU
boolsig e_Cnd 'ex_mem_next->takebranch' # Does condition hold?
wordsig e_dstE 'ex_mem_next->deste' # dstE (possibly modified to be RNONE)
##### Pipeline Register M #########################
wordsig M_stat 'ex_mem_curr->status' # Instruction status
wordsig M_icode 'ex_mem_curr->icode' # Instruction code
wordsig M_ifun 'ex_mem_curr->ifun' # Instruction function
wordsig M_valA 'ex_mem_curr->vala' # Source A value
wordsig M_dstE 'ex_mem_curr->deste' # Destination E register ID
wordsig M_valE 'ex_mem_curr->vale' # ALU E value
wordsig M_dstM 'ex_mem_curr->destm' # Destination M register ID
boolsig M_Cnd 'ex_mem_curr->takebranch' # Condition flag
boolsig dmem_error 'dmem_error' # Error signal from instruction memory
## LF: Carry srcA up to pipeline register M
wordsig M_srcA 'ex_mem_curr->srca' # Source A register ID
##### Intermediate Values in Memory Stage ##########################
wordsig m_valM 'mem_wb_next->valm' # valM generated by memory
wordsig m_stat 'mem_wb_next->status' # stat (possibly modified to be SADR)
##### Pipeline Register W ##########################################
wordsig W_stat 'mem_wb_curr->status' # Instruction status
wordsig W_icode 'mem_wb_curr->icode' # Instruction code
wordsig W_dstE 'mem_wb_curr->deste' # Destination E register ID
wordsig W_valE 'mem_wb_curr->vale' # ALU E value
wordsig W_dstM 'mem_wb_curr->destm' # Destination M register ID
wordsig W_valM 'mem_wb_curr->valm' # Memory M value
####################################################################
# Control Signal Definitions. #
####################################################################
################ Fetch Stage ###################################
## What address should instruction be fetched at
word f_pc = [# Mispredicted branch. Fetch at incremented PCM_icode == IJXX && !M_Cnd : M_valA;# Completion of RET instructionW_icode == IRET : W_valM;# Default: Use predicted value of PC1 : F_predPC;
];
## Determine icode of fetched instruction
word f_icode = [imem_error : INOP;1: imem_icode;
];
# Determine ifun
word f_ifun = [imem_error : FNONE;1: imem_ifun;
];
# Is instruction valid?
bool instr_valid = f_icode in { INOP, IHALT, IRRMOVQ, IIRMOVQ, IRMMOVQ, IMRMOVQ,IOPQ, IJXX, ICALL, IRET, IPUSHQ, IPOPQ };
# Determine status code for fetched instruction
word f_stat = [imem_error: SADR;!instr_valid : SINS;f_icode == IHALT : SHLT;1 : SAOK;
];
# Does fetched instruction require a regid byte?
bool need_regids =f_icode in { IRRMOVQ, IOPQ, IPUSHQ, IPOPQ, IIRMOVQ, IRMMOVQ, IMRMOVQ };
# Does fetched instruction require a constant word?
bool need_valC =f_icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ, IJXX, ICALL };
# Predict next value of PC
word f_predPC = [f_icode in { IJXX, ICALL } : f_valC;1 : f_valP;
];
################ Decode Stage ######################################
## What register should be used as the A source?
word d_srcA = [D_icode in { IRRMOVQ, IRMMOVQ, IOPQ, IPUSHQ } : D_rA;D_icode in { IPOPQ, IRET } : RRSP;1 : RNONE; # Don't need register
];
## What register should be used as the B source?
word d_srcB = [D_icode in { IOPQ, IRMMOVQ, IMRMOVQ } : D_rB;D_icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;1 : RNONE; # Don't need register
];
## What register should be used as the E destination?
word d_dstE = [D_icode in { IRRMOVQ, IIRMOVQ, IOPQ} : D_rB;D_icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;1 : RNONE; # Don't write any register
];
## What register should be used as the M destination?
word d_dstM = [D_icode in { IMRMOVQ, IPOPQ } : D_rA;1 : RNONE; # Don't write any register
];
## What should be the A value?
## Forward into decode stage for valA
word d_valA = [D_icode in { ICALL, IJXX } : D_valP; # Use incremented PCd_srcA == e_dstE : e_valE; # Forward valE from executed_srcA == M_dstM : m_valM; # Forward valM from memoryd_srcA == M_dstE : M_valE; # Forward valE from memoryd_srcA == W_dstM : W_valM; # Forward valM from write backd_srcA == W_dstE : W_valE; # Forward valE from write back1 : d_rvalA; # Use value read from register file
];
word d_valB = [d_srcB == e_dstE : e_valE; # Forward valE from executed_srcB == M_dstM : m_valM; # Forward valM from memoryd_srcB == M_dstE : M_valE; # Forward valE from memoryd_srcB == W_dstM : W_valM; # Forward valM from write backd_srcB == W_dstE : W_valE; # Forward valE from write back1 : d_rvalB; # Use value read from register file
];
################ Execute Stage #####################################
## Select input A to ALU
word aluA = [E_icode in { IRRMOVQ, IOPQ } : E_valA;E_icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ } : E_valC;E_icode in { ICALL, IPUSHQ } : -8;E_icode in { IRET, IPOPQ } : 8;# Other instructions don't need ALU
];
## Select input B to ALU
word aluB = [E_icode in { IRMMOVQ, IMRMOVQ, IOPQ, ICALL, IPUSHQ, IRET, IPOPQ } : E_valB;E_icode in { IRRMOVQ, IIRMOVQ } : 0;# Other instructions don't need ALU
];
## Set the ALU function
word alufun = [E_icode == IOPQ : E_ifun;1 : ALUADD;
];
## Should the condition codes be updated?
bool set_cc = E_icode == IOPQ &&# State changes only during normal operation!m_stat in { SADR, SINS, SHLT } && !W_stat in { SADR, SINS, SHLT };
## Generate valA in execute stage
## LB: With load forwarding, want to insert valM
## from memory stage when appropriate
## Here it is set to the default used in the normal pipeline
word e_valA = [E_icode in { IRMMOVQ, IPUSHQ } && E_srcA == M_dstM : m_valM;1 : E_valA; # Use valA from stage pipe register
];
## Set dstE to RNONE in event of not-taken conditional move
word e_dstE = [E_icode == IRRMOVQ && !e_Cnd : RNONE;1 : E_dstE;
];
################ Memory Stage ######################################
## Select memory address
word mem_addr = [M_icode in { IRMMOVQ, IPUSHQ, ICALL, IMRMOVQ } : M_valE;M_icode in { IPOPQ, IRET } : M_valA;# Other instructions don't need address
];
## Set read control signal
bool mem_read = M_icode in { IMRMOVQ, IPOPQ, IRET };
## Set write control signal
bool mem_write = M_icode in { IRMMOVQ, IPUSHQ, ICALL };
#/* $begin pipe-m_stat-hcl */
## Update the status
word m_stat = [dmem_error : SADR;1 : M_stat;
];
#/* $end pipe-m_stat-hcl */
## Set E port register ID
word w_dstE = W_dstE;
## Set E port value
word w_valE = W_valE;
## Set M port register ID
word w_dstM = W_dstM;
## Set M port value
word w_valM = W_valM;
## Update processor status
word Stat = [W_stat == SBUB : SAOK;1 : W_stat;
];
################ Pipeline Register Control #########################
# Should I stall or inject a bubble into Pipeline Register F?
# At most one of these can be true.
bool F_bubble = 0;
bool F_stall =# Conditions for a load/use hazard## Set this to the new load/use conditionE_icode in { IMRMOVQ, IPOPQ } &&(E_dstM == d_srcB ||(E_dstM == d_srcA && !(D_icode in { IRMMOVQ, IPUSHQ }))) ||# Stalling at fetch while ret passes through pipelineIRET in { D_icode, E_icode, M_icode };
# Should I stall or inject a bubble into Pipeline Register D?
# At most one of these can be true.
bool D_stall = # Conditions for a load/use hazard## Set this to the new load/use conditionE_icode in { IMRMOVQ, IPOPQ } &&(E_dstM == d_srcB ||(E_dstM == d_srcA && !(D_icode in { IRMMOVQ, IPUSHQ })));
bool D_bubble =# Mispredicted branch(E_icode == IJXX && !e_Cnd) ||# Stalling at fetch while ret passes through pipeline# but not condition for a load/use hazard!(E_icode in { IMRMOVQ, IPOPQ } &&(E_dstM == d_srcB ||(E_dstM == d_srcA && !(D_icode in { IRMMOVQ, IPUSHQ })))) &&IRET in { D_icode, E_icode, M_icode };
# Should I stall or inject a bubble into Pipeline Register E?
# At most one of these can be true.
bool E_stall = 0;
bool E_bubble =# Mispredicted branch(E_icode == IJXX && !e_Cnd) ||# Conditions for a load/use hazard## Set this to the new load/use conditionE_icode in { IMRMOVQ, IPOPQ } &&(E_dstM == d_srcB ||(E_dstM == d_srcA && !(D_icode in { IRMMOVQ, IPUSHQ })));
# Should I stall or inject a bubble into Pipeline Register M?
# At most one of these can be true.
bool M_stall = 0;
# Start injecting bubbles as soon as exception passes through memory stage
bool M_bubble = m_stat in { SADR, SINS, SHLT } || W_stat in { SADR, SINS, SHLT };
# Should I stall or inject a bubble into Pipeline Register W?
bool W_stall = W_stat in { SADR, SINS, SHLT };
bool W_bubble = 0;
#/* $end pipe-all-hcl */P58
#/* $begin pipe-all-hcl */
####################################################################
# HCL Description of Control for Pipelined Y86-64 Processor #
# Copyright (C) Randal E. Bryant, David R. O'Hallaron, 2014 #
####################################################################
## Your task is to modify the design so that on any cycle, only
## one of the two possible (valE and valM) register writes will occur.
## This requires special handling of the popq instruction.
## Overall strategy: IPOPQ passes through pipe,
## treated as stack pointer increment, but not incrementing the PC
## On refetch, modify fetched icode to indicate an instruction "IPOP2",
## which reads from memory.
## This requires modifying the definition of f_icode
## and lots of other changes. Relevant positions to change
## are indicated by comments starting with keyword "1W".
####################################################################
# C Include's. Don't alter these #
####################################################################
quote '#include <stdio.h>'
quote '#include "isa.h"'
quote '#include "pipeline.h"'
quote '#include "stages.h"'
quote '#include "sim.h"'
quote 'int sim_main(int argc, char *argv[]);'
quote 'int main(int argc, char *argv[]){return sim_main(argc,argv);}'
####################################################################
# Declarations. Do not change/remove/delete any of these #
####################################################################
##### Symbolic representation of Y86-64 Instruction Codes #############
wordsig INOP 'I_NOP'
wordsig IHALT 'I_HALT'
wordsig IRRMOVQ 'I_RRMOVQ'
wordsig IIRMOVQ 'I_IRMOVQ'
wordsig IRMMOVQ 'I_RMMOVQ'
wordsig IMRMOVQ 'I_MRMOVQ'
wordsig IOPQ 'I_ALU'
wordsig IJXX 'I_JMP'
wordsig ICALL 'I_CALL'
wordsig IRET 'I_RET'
wordsig IPUSHQ 'I_PUSHQ'
wordsig IPOPQ 'I_POPQ'
# 1W: Special instruction code for second try of popq
wordsig IPOP2 'I_POP2'
##### Symbolic represenations of Y86-64 function codes #####
wordsig FNONE 'F_NONE' # Default function code
##### Symbolic representation of Y86-64 Registers referenced #####
wordsig RRSP 'REG_RSP' # Stack Pointer
wordsig RNONE 'REG_NONE' # Special value indicating "no register"
##### ALU Functions referenced explicitly ##########################
wordsig ALUADD 'A_ADD' # ALU should add its arguments
##### Possible instruction status values #####
wordsig SBUB 'STAT_BUB' # Bubble in stage
wordsig SAOK 'STAT_AOK' # Normal execution
wordsig SADR 'STAT_ADR' # Invalid memory address
wordsig SINS 'STAT_INS' # Invalid instruction
wordsig SHLT 'STAT_HLT' # Halt instruction encountered
##### Signals that can be referenced by control logic ##############
##### Pipeline Register F ##########################################
wordsig F_predPC 'pc_curr->pc' # Predicted value of PC
##### Intermediate Values in Fetch Stage ###########################
wordsig imem_icode 'imem_icode' # icode field from instruction memory
wordsig imem_ifun 'imem_ifun' # ifun field from instruction memory
wordsig f_icode 'if_id_next->icode' # (Possibly modified) instruction code
wordsig f_ifun 'if_id_next->ifun' # Fetched instruction function
wordsig f_valC 'if_id_next->valc' # Constant data of fetched instruction
wordsig f_valP 'if_id_next->valp' # Address of following instruction
## 1W: Provide access to the PC value for the current instruction
wordsig f_pc 'f_pc' # Address of fetched instruction
boolsig imem_error 'imem_error' # Error signal from instruction memory
boolsig instr_valid 'instr_valid' # Is fetched instruction valid?
##### Pipeline Register D ##########################################
wordsig D_icode 'if_id_curr->icode' # Instruction code
wordsig D_rA 'if_id_curr->ra' # rA field from instruction
wordsig D_rB 'if_id_curr->rb' # rB field from instruction
wordsig D_valP 'if_id_curr->valp' # Incremented PC
##### Intermediate Values in Decode Stage #########################
wordsig d_srcA 'id_ex_next->srca' # srcA from decoded instruction
wordsig d_srcB 'id_ex_next->srcb' # srcB from decoded instruction
wordsig d_rvalA 'd_regvala' # valA read from register file
wordsig d_rvalB 'd_regvalb' # valB read from register file
##### Pipeline Register E ##########################################
wordsig E_icode 'id_ex_curr->icode' # Instruction code
wordsig E_ifun 'id_ex_curr->ifun' # Instruction function
wordsig E_valC 'id_ex_curr->valc' # Constant data
wordsig E_srcA 'id_ex_curr->srca' # Source A register ID
wordsig E_valA 'id_ex_curr->vala' # Source A value
wordsig E_srcB 'id_ex_curr->srcb' # Source B register ID
wordsig E_valB 'id_ex_curr->valb' # Source B value
wordsig E_dstE 'id_ex_curr->deste' # Destination E register ID
wordsig E_dstM 'id_ex_curr->destm' # Destination M register ID
##### Intermediate Values in Execute Stage #########################
wordsig e_valE 'ex_mem_next->vale' # valE generated by ALU
boolsig e_Cnd 'ex_mem_next->takebranch' # Does condition hold?
wordsig e_dstE 'ex_mem_next->deste' # dstE (possibly modified to be RNONE)
##### Pipeline Register M #########################
wordsig M_stat 'ex_mem_curr->status' # Instruction status
wordsig M_icode 'ex_mem_curr->icode' # Instruction code
wordsig M_ifun 'ex_mem_curr->ifun' # Instruction function
wordsig M_valA 'ex_mem_curr->vala' # Source A value
wordsig M_dstE 'ex_mem_curr->deste' # Destination E register ID
wordsig M_valE 'ex_mem_curr->vale' # ALU E value
wordsig M_dstM 'ex_mem_curr->destm' # Destination M register ID
boolsig M_Cnd 'ex_mem_curr->takebranch' # Condition flag
boolsig dmem_error 'dmem_error' # Error signal from instruction memory
##### Intermediate Values in Memory Stage ##########################
wordsig m_valM 'mem_wb_next->valm' # valM generated by memory
wordsig m_stat 'mem_wb_next->status' # stat (possibly modified to be SADR)
##### Pipeline Register W ##########################################
wordsig W_stat 'mem_wb_curr->status' # Instruction status
wordsig W_icode 'mem_wb_curr->icode' # Instruction code
wordsig W_dstE 'mem_wb_curr->deste' # Destination E register ID
wordsig W_valE 'mem_wb_curr->vale' # ALU E value
wordsig W_dstM 'mem_wb_curr->destm' # Destination M register ID
wordsig W_valM 'mem_wb_curr->valm' # Memory M value
####################################################################
# Control Signal Definitions. #
####################################################################
################ Fetch Stage ###################################
## What address should instruction be fetched at
word f_pc = [# Mispredicted branch. Fetch at incremented PCM_icode == IJXX && !M_Cnd : M_valA;# Completion of RET instructionW_icode == IRET : W_valM;# Default: Use predicted value of PC1 : F_predPC;
];
## Determine icode of fetched instruction
## 1W: To split ipopq into two cycles, need to be able to
## modify value of icode,
## so that it will be IPOP2 when fetched for second time.
word f_icode = [imem_error : INOP;D_icode == IPOPQ : IPOP2;1: imem_icode;
];
# Determine ifun
word f_ifun = [imem_error : FNONE;1: imem_ifun;
];
# Is instruction valid?
bool instr_valid = f_icode in { INOP, IHALT, IRRMOVQ, IIRMOVQ, IRMMOVQ, IMRMOVQ,IOPQ, IJXX, ICALL, IRET, IPUSHQ, IPOPQ, IPOP2 };
# Determine status code for fetched instruction
word f_stat = [imem_error: SADR;!instr_valid : SINS;f_icode == IHALT : SHLT;1 : SAOK;
];
# Does fetched instruction require a regid byte?
bool need_regids =f_icode in { IRRMOVQ, IOPQ, IPUSHQ, IPOPQ, IIRMOVQ, IRMMOVQ, IMRMOVQ, IPOP2 };
# Does fetched instruction require a constant word?
bool need_valC =f_icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ, IJXX, ICALL };
# Predict next value of PC
word f_predPC = [f_icode in { IJXX, ICALL } : f_valC;## 1W: Want to refetch popq one timef_icode == IPOPQ : f_pc;1 : f_valP;
];
################ Decode Stage ######################################
## 1W: Strategy. Decoding of popq rA should be treated the same
## as would iaddq $8, %rsp
## Decoding of pop2 rA treated same as mrmovq -8(%rsp), rA
## What register should be used as the A source?
word d_srcA = [D_icode in { IRRMOVQ, IRMMOVQ, IOPQ, IPUSHQ } : D_rA;D_icode in { IRET } : RRSP;1 : RNONE; # Don't need register
];
## What register should be used as the B source?
word d_srcB = [D_icode in { IOPQ, IRMMOVQ, IMRMOVQ } : D_rB;D_icode in { IPUSHQ, IPOPQ, IPOP2, ICALL, IRET } : RRSP;1 : RNONE; # Don't need register
];
## What register should be used as the E destination?
word d_dstE = [D_icode in { IRRMOVQ, IIRMOVQ, IOPQ} : D_rB;D_icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;1 : RNONE; # Don't write any register
];
## What register should be used as the M destination?
word d_dstM = [D_icode in { IMRMOVQ, IPOP2 } : D_rA;1 : RNONE; # Don't write any register
];
## What should be the A value?
## Forward into decode stage for valA
word d_valA = [D_icode in { ICALL, IJXX } : D_valP; # Use incremented PCd_srcA == e_dstE : e_valE; # Forward valE from executed_srcA == M_dstM : m_valM; # Forward valM from memoryd_srcA == M_dstE : M_valE; # Forward valE from memoryd_srcA == W_dstM : W_valM; # Forward valM from write backd_srcA == W_dstE : W_valE; # Forward valE from write back1 : d_rvalA; # Use value read from register file
];
word d_valB = [d_srcB == e_dstE : e_valE; # Forward valE from executed_srcB == M_dstM : m_valM; # Forward valM from memoryd_srcB == M_dstE : M_valE; # Forward valE from memoryd_srcB == W_dstM : W_valM; # Forward valM from write backd_srcB == W_dstE : W_valE; # Forward valE from write back1 : d_rvalB; # Use value read from register file
];
################ Execute Stage #####################################
## Select input A to ALU
word aluA = [E_icode in { IRRMOVQ, IOPQ } : E_valA;E_icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ } : E_valC;E_icode in { ICALL, IPUSHQ, IPOP2 } : -8;E_icode in { IRET, IPOPQ } : 8;# Other instructions don't need ALU
];
## Select input B to ALU
word aluB = [E_icode in { IRMMOVQ, IMRMOVQ, IOPQ, ICALL, IPUSHQ, IRET, IPOPQ, IPOP2 } : E_valB;E_icode in { IRRMOVQ, IIRMOVQ } : 0;# Other instructions don't need ALU
];
## Set the ALU function
word alufun = [E_icode == IOPQ : E_ifun;1 : ALUADD;
];
## Should the condition codes be updated?
bool set_cc = E_icode == IOPQ &&# State changes only during normal operation!m_stat in { SADR, SINS, SHLT } && !W_stat in { SADR, SINS, SHLT };
## Generate valA in execute stage
word e_valA = E_valA; # Pass valA through stage
## Set dstE to RNONE in event of not-taken conditional move
word e_dstE = [E_icode == IRRMOVQ && !e_Cnd : RNONE;1 : E_dstE;
];
################ Memory Stage ######################################
## Select memory address
word mem_addr = [M_icode in { IRMMOVQ, IPUSHQ, ICALL, IMRMOVQ, IPOP2 } : M_valE;M_icode in { IRET } : M_valA;# Other instructions don't need address
];
## Set read control signal
bool mem_read = M_icode in { IMRMOVQ, IRET, IPOP2 };
## Set write control signal
bool mem_write = M_icode in { IRMMOVQ, IPUSHQ, ICALL };
#/* $begin pipe-m_stat-hcl */
## Update the status
word m_stat = [dmem_error : SADR;1 : M_stat;
];
#/* $end pipe-m_stat-hcl */
################ Write back stage ##################################
## 1W: For this problem, we introduce a multiplexor that merges
## valE and valM into a single value for writing to register port E.
## DO NOT CHANGE THIS LOGIC
## Merge both write back sources onto register port E
## Set E port register ID
word w_dstE = [## writing from valMW_dstM != RNONE : W_dstM;1: W_dstE;
];
## Set E port value
word w_valE = [W_dstM != RNONE : W_valM;1: W_valE;
];
## Disable register port M
## Set M port register ID
word w_dstM = RNONE;
## Set M port value
word w_valM = 0;
## Update processor status
word Stat = [W_stat == SBUB : SAOK;1 : W_stat;
];
################ Pipeline Register Control #########################
# Should I stall or inject a bubble into Pipeline Register F?
# At most one of these can be true.
bool F_bubble = 0;
bool F_stall =# Conditions for a load/use hazardE_icode in { IMRMOVQ, IPOP2 } &&E_dstM in { d_srcA, d_srcB } ||# Stalling at fetch while ret passes through pipelineIRET in { D_icode, E_icode, M_icode };
# Should I stall or inject a bubble into Pipeline Register D?
# At most one of these can be true.
bool D_stall = # Conditions for a load/use hazardE_icode in { IMRMOVQ, IPOP2 } &&E_dstM in { d_srcA, d_srcB };
bool D_bubble =# Mispredicted branch(E_icode == IJXX && !e_Cnd) ||# Stalling at fetch while ret passes through pipeline# but not condition for a load/use hazard!(E_icode in { IMRMOVQ, IPOP2 } && E_dstM in { d_srcA, d_srcB }) &&# 1W: This condition will changeIRET in { D_icode, E_icode, M_icode };
# Should I stall or inject a bubble into Pipeline Register E?
# At most one of these can be true.
bool E_stall = 0;
bool E_bubble =# Mispredicted branch(E_icode == IJXX && !e_Cnd) ||# Conditions for a load/use hazardE_icode in { IMRMOVQ, IPOP2 } &&E_dstM in { d_srcA, d_srcB};
# Should I stall or inject a bubble into Pipeline Register M?
# At most one of these can be true.
bool M_stall = 0;
# Start injecting bubbles as soon as exception passes through memory stage
bool M_bubble = m_stat in { SADR, SINS, SHLT } || W_stat in { SADR, SINS, SHLT };
# Should I stall or inject a bubble into Pipeline Register W?
bool W_stall = W_stat in { SADR, SINS, SHLT };
bool W_bubble = 0;
#/* $end pipe-all-hcl */P59
4.47的更好，命中率更高。
第四章 完
《CSAPP》（第3版）答案（第四章）相关推荐
- 计算机理论导引第三版答案第四章,《计算理论导引》第四章：可判定性-学习笔记 | 诟屍...
第四章:可判定性 4 Decidability 关于其他章节的内容,请点这:<计算理论导引>学习笔记 4.1 Decidable Languages 几个可判定的语言 acceptance ...
- 数据结构c语言版第四章题库,严蔚敏《数据结构(c语言版)习题集》答案第四章 串...
严蔚敏<数据结构(c语言版)习题集>答案第四章 串 第四章 串 4.10 void String_Reverse(Stringtype s,Stringtype &r)//求s的逆 ...
- 计算机文化基础（高职高专版 第十一版）第四章答案
1.简述工作簿.工作表.单元格之间的关系. 工作簿:指在Excel中用来存储并处理数据的文件,扩展名是.xlsx.由一个或多个工作表组成.工作表:是由行和列交叉排列的二维表格,也称电子表格,用于组织和 ...
- 计算机网络（谢希仁-第八版）第四章习题全解
4-01 网络层向上提供的服务有哪两种?试比较其优缺点? 虚电路服务和数据报服务. 虚电路 优点: 1.可以提供可靠的通信服务 2.因为数据是沿着建立的虚电路进行传输的,因此分组的首部不需要携带完整的 ...
- 【Python学习笔记—保姆版】第四章—关于Pandas、数据准备、数据处理、数据分析、数据可视化
第四章 欢迎访问我搞事情的[知乎账号]:Coffee 以及我的[B站漫威剪辑账号]:VideosMan 若我的笔记对你有帮助,请用小小的手指,点一个大大的赞哦. #编译器使用的是sypder,其中&q ...
- 李含光《C语言程序设计教程》答案第一——四章
李含光<C语言程序设计教程>答案第一--四章 第一章 单选 ACDCB 填空 函数 主函数或main函数 scanf printf 第二章 单选 CBCCC CDCDC D 填空 1 26 ...
- 操作系统课后答案第四章
**操作系统课后答案** 第四章 存储器管理 1.为什么要配置层次式存储器? 答:设置多个存储器可以使存储器两端的硬件能并行工作:采用多级存储系统,特别是Cache 技术,是减轻存储器带宽对系统性能影 ...
- 朱长江《偏微分方程简明教程》答案第四章部分
偏微分方程简明教程答案 第四章 方程的导出及定解问题的提法 习题4.1 4.1.1 4.1.3 4.1.4 习题4.2 4.2.1 4.2.2 4.2.5 4.2.8 习题4.3 习题4.4 4.4. ...
- Timo学习笔记 ：Python基础教程（第三版）第四章 当索引行不通时
第四章 当索引行不通时 Timo学习笔记 :Python基础教程(第三版)第三章 使用字符串 这是word编辑的最后一章笔记,第五章开始将直接用这个模板记录. 本章笔记很少,也很简单.很多方法可以到要 ...
- 计算机原理第四章答案,计算机组成原理习题答案第四章
<计算机组成原理习题答案第四章>由会员分享,可在线阅读,更多相关<计算机组成原理习题答案第四章(6页珍藏版)>请在人人文库网上搜索. 1.计算机组成原理习题答案第四章1.指令长 ...
最新文章
- mac 搭建php wamp,Linux,Windows,Mac平台php环境配置
- python程序在安卓上如何运行-在 android 上运行 python 的方法
- Docker常用命令操作——1）、镜像操作；2）、容器操作
- 微信路况会不会超越地图导航？
- 看完就能知道渗透测试的技术结构
- vboxdrv.sh failed modprobe vboxdrv failed. Please use 'dmesg' to find out why
- Docker: vmware企业级docker镜像私服--Harbor的搭建
- 线上CPU飚高（死循环，死锁……）？帮你迅速定位代码位置
- python qq签到_Yii Framework 中文网每天签到 Python 脚本
- 思杰彻底简化浏览器应用的安全交付
- 使用 TensorFlow 做文本情感分析
- 【Linux】linux经常使用基本命令
- 实现截图页面并导出word
- C语言编写的爱心代码
- 1到10加法创新图片-走迷宫_“小火锅+关东煮”，呷哺呷哺又创新模式！客单提到110元！...
- 计算机键入命令,Win7系统安装软件提示命令行语法错误键入“ 命令/？”怎么办...
- 计算机卸载应用程序的步骤,Win10系统下卸载应用程序的步骤
- 英语计算机单词mp3,[听单词] 计算机专业英语词汇音频51,计算机英语单词MP3
- java写入文件怎么换行，经验分享
- [渝粤教育] 西南科技大学 网站建设与维护 在线考试复习资料