arm反汇编 之数组
#include <stdio.h>
/*
*(a+1）就是a[1]，*(ptr-1)就是a[4],执行结果是2，5
&a+1不是首地址+1，系统会认为加一个a数组的偏移，是偏移了一个数组的大小（本例是5个int）
int *ptr=(int *)(&a+1);
则ptr实际是&(a[5]),也就是a+5
原因如下：
&a是数组指针，其类型为 int (*)[5];
而指针加1要根据指针类型加上一定的值，不同类型的指针+1之后增加的大小不同。
a是长度为5的int数组指针，所以要加 5*sizeof(int)
所以ptr实际是a[5]
但是prt与(&a+1)类型是不一样的(这点很重要)
所以prt-1只会减去sizeof(int*)
a,&a的地址是一样的，但意思不一样
a是数组首地址，也就是a[0]的地址，&a是对象（数组）首地址，
a+1是数组下一元素的地址，即a[1],&a+1是下一个对象的地址，即a[5].
*/
int array1()
{
int ar[3][4] = {{3,2,1,0},{3,2,1,0},{3,2,1,0}};
int array[100];
array[0] = 1;
array[1] = 1;
array[2] = 1;
array[3] = 1;
array[4] = 1;
array[5] = 1;
array[6] = 1;
array[7] = 1;
array[8] = 1;
array[9] = 1;
}
int array2()
{
int ar[10];
int aw[10];
char ac[10];
}
int array3()
{
int ar[10];
int aw[10];
char ac[10];
ar[0] = 100;
aw[0] = 50;
ac[0] = 'a';
ac[1] = 'b';
ac[2] = 'c';
ac[3] = 'd';
ac[4] = 'e';
ac[5] = 'f';
ac[6] = '\0';
}
void array4()
{
int ar[3][4];
ar[0][0] = 1;
ar[0][1] = 2;
ar[0][2] = 3;
ar[0][3] = 4;
ar[1][0] = 5;
ar[1][1] = 6;
ar[1][2] = 7;
ar[1][3] = 8;
}
#define COLS 4
int sum2d(int ar[][COLS], int rows);
int sum (int ar[], int n);
int aaa()
{
int total1, total2, total3;
int *pt1;
int (*pt2)[COLS];
pt1 = (int [2]) {10, 20};
pt2 = (int [2][COLS]) { {1, 2, 3, -9}, {4, 5, 6,-8} };
total1 = sum(pt1, 2);
total2 = sum2d(pt2, 2);
total3 = sum((int[]){4,4,4,5,5,5},6);
printf("total1 = %d\n", total1); // 30
printf("total2 = %d\n", total2); // 4
printf("total3 = %d\n", total3); // 27
}
int sum(int ar[], int n)
{
int i;
int total = 0;
for (i = 0; i < n; i++)
total += ar[i];
return total;
}
int sum2d(int ar[][COLS], int rows)
{
int r;
int c;
int tot = 0;
for (r = 0; r < rows; r++)
for (c = 0; c < COLS; c++)
tot += ar[r][c];
return tot;
}
int bbb()
{
int row = 3, col = 4;
int ary[row][col];
int array(int col, int row, int ary[col][row]);
int arra2(int ary[col][row], int col, int row); // not VLA
}
int array_cal(void)
{
int a[5]={1,2,3,4,9};
int *ptr1 = (int*)(&a + 1);
int *ptr2 = (int*)((int)a + 1);
int temp = (int)(&a + 1 ); // &a+1 = &a + sizeof(a) = &a + 5 * sizeof(int),也就是下一个数组的首地址.
//printf("temp - : %d, 0x%x, %x, 0x%x\n", temp, *ptr1, ptr1[-1], *ptr2);
printf("a - 0x%x\n", a); // 0x859033c0
printf("a = 0x%x\n", &a); // 0x859033c0
printf("a - 0x%x\n", a+1); // 0x859033c4 0x859033c0+sizeof(int) = 0x859033c0+4 = 0x859033c4
printf("a = 0x%x\n", &a+1); // 0x859033d4 0x859033d4 - 0x859033c0 = 0x14 = 20 = sizeof(a)
printf("temp - 0x%x\n", temp); // 0x859033d4 &a + 1
printf("temp = %p\n", temp); // 0x859033d4 &a + 1
printf("temp = %p\n\n", &temp); // 0x7ffd859033ac temp self address
printf("ptr1 - 0x%x, \n", *ptr1); // 0x0 &a+1 value
printf("ptr1 - %p\n", *ptr1); // (nil) 非法地址. 因为是空值，所以没有地址.
printf("ptr1 - 0x%x\n", ptr1); // 0x859033d4 &a+1 ---> %x
printf("ptr1 - %p\n", ptr1); // 0x7ffd859033d4 &a+1 ---> %p
printf("ptr1 - %p\n\n", &ptr1); // 0x7ffd859033b0 ptr1 self address ---> %p
printf("ptr1 - : 0x%x\n", ptr1[-1]); // 0x9
//printf("ptr2 - : 0x%x\n", *ptr2); // Segmentation fault 取非法地址值
//printf("ptr2 - %p, \n", *ptr2); // Segmentation fault 非法地址
printf("ptr2 - %p\n", ptr2); // 0xffffffff859033c1 指向的地址。0x859033c0 + 1 = 859033c1
printf("ptr2 - %p\n\n", &ptr2); // 0x7ffd859033b8 ptr2 self address ---> %p
return 0;
}
int ccc(void)
{
int array[10] = {11, 15, 20, 25, 30};
int *p;
p = &array[2];
printf("%d\n", *p); // 20 = array[2]
printf("%d\n", p[-1]); // 15 = array[1]
printf("%d\n", *(p-2)); // 11 = array[1] *(p-2) = p[-2]
printf("%d\n", array[9]); // 0
return 0;
}
int main()
{
aaa();
bbb();
array1();
array2();
array3();
array4();
array_cal();
ccc();
return 0;
}
arm 反汇编
/*
x29 0x7ffffff410 549755810832
x30 0x400c5c 4197468
sp 0x7ffffff410 0x7ffffff410
pc 0x4005fc 0x4005fc
*/
00000000004005fc <array1>:
4005fc: d10703ff sub sp, sp, #0x1c0
400600: 90000000 adrp x0, 400000 <_init-0x480>
400604: 9134c001 add x1, x0, #0xd30 // x1 = 0x400d30
400608: 910643e0 add x0, sp, #0x190 // x0 = 0x7ffffff3e0
40060c: a9400c22 ldp x2, x3, [x1] // x2 = 0x200000003, x3 = 0x1
400610: a9000c02 stp x2, x3, [x0]
400614: a9410c22 ldp x2, x3, [x1, #16] // x2 = 0x200000003, x3 = 0x1
400618: a9010c02 stp x2, x3, [x0, #16]
40061c: a9420821 ldp x1, x2, [x1, #32] // x1 = 0x200000003, x2 = 0x1
400620: a9020801 stp x1, x2, [x0, #32]
400624: 52800020 mov w0, #0x1 // #1
400628: b90003e0 str w0, [sp]
40062c: 52800020 mov w0, #0x1 // #1
400630: b90007e0 str w0, [sp, #4]
400634: 52800020 mov w0, #0x1 // #1
400638: b9000be0 str w0, [sp, #8]
40063c: 52800020 mov w0, #0x1 // #1
400640: b9000fe0 str w0, [sp, #12]
400644: 52800020 mov w0, #0x1 // #1
400648: b90013e0 str w0, [sp, #16]
40064c: 52800020 mov w0, #0x1 // #1
400650: b90017e0 str w0, [sp, #20]
400654: 52800020 mov w0, #0x1 // #1
400658: b9001be0 str w0, [sp, #24]
40065c: 52800020 mov w0, #0x1 // #1
400660: b9001fe0 str w0, [sp, #28]
400664: 52800020 mov w0, #0x1 // #1
400668: b90023e0 str w0, [sp, #32]
40066c: 52800020 mov w0, #0x1 // #1
400670: b90027e0 str w0, [sp, #36]
400674: d503201f nop
400678: 910703ff add sp, sp, #0x1c0
40067c: d65f03c0 ret
0000000000400680 <array2>:
400680: d10183ff sub sp, sp, #0x60
400684: d503201f nop
400688: 910183ff add sp, sp, #0x60
40068c: d65f03c0 ret
/*
x29 0x7ffffff410 549755810832
x30 0x400c64 4197476
sp 0x7ffffff410 0x7ffffff410
pc 0x400690 0x400690
*/
0000000000400690 <array3>:
400690: d10183ff sub sp, sp, #0x60
400694: 52800c80 mov w0, #0x64 // #100
400698: b9003be0 str w0, [sp, #56]
40069c: 52800640 mov w0, #0x32 // #50
4006a0: b90013e0 str w0, [sp, #16]
4006a4: 52800c20 mov w0, #0x61 // #97
4006a8: 390003e0 strb w0, [sp]
4006ac: 52800c40 mov w0, #0x62 // #98
4006b0: 390007e0 strb w0, [sp, #1]
4006b4: 52800c60 mov w0, #0x63 // #99
4006b8: 39000be0 strb w0, [sp, #2]
4006bc: 52800c80 mov w0, #0x64 // #100
4006c0: 39000fe0 strb w0, [sp, #3]
4006c4: 52800ca0 mov w0, #0x65 // #101
4006c8: 390013e0 strb w0, [sp, #4]
4006cc: 52800cc0 mov w0, #0x66 // #102
4006d0: 390017e0 strb w0, [sp, #5]
4006d4: 39001bff strb wzr, [sp, #6]
4006d8: d503201f nop
4006dc: 910183ff add sp, sp, #0x60
4006e0: d65f03c0 ret
00000000004006e4 <array4>:
4006e4: d100c3ff sub sp, sp, #0x30
4006e8: 52800020 mov w0, #0x1 // #1
4006ec: b90003e0 str w0, [sp]
4006f0: 52800040 mov w0, #0x2 // #2
4006f4: b90007e0 str w0, [sp, #4]
4006f8: 52800060 mov w0, #0x3 // #3
4006fc: b9000be0 str w0, [sp, #8]
400700: 52800080 mov w0, #0x4 // #4
400704: b9000fe0 str w0, [sp, #12]
400708: 528000a0 mov w0, #0x5 // #5
40070c: b90013e0 str w0, [sp, #16]
400710: 528000c0 mov w0, #0x6 // #6
400714: b90017e0 str w0, [sp, #20]
400718: 528000e0 mov w0, #0x7 // #7
40071c: b9001be0 str w0, [sp, #24]
400720: 52800100 mov w0, #0x8 // #8
400724: b9001fe0 str w0, [sp, #28]
400728: d503201f nop
40072c: 9100c3ff add sp, sp, #0x30
400730: d65f03c0 ret
0000000000400734 <aaa>:
400734: a9b97bfd stp x29, x30, [sp, #-112]!
400738: 910003fd mov x29, sp
40073c: 52800140 mov w0, #0xa // #10
400740: b90013a0 str w0, [x29, #16] // [x29+16]=10
400744: 52800280 mov w0, #0x14 // #20
400748: b90017a0 str w0, [x29, #20] // [x29+20]=20
40074c: 910043a0 add x0, x29, #0x10 // x0=x29+0x10 = 0x7ffffff3b0
400750: f90037a0 str x0, [x29, #104] // [x29+104]=x29+0x10 --> 0x7ffffff408:0x7ffffff3b0
400754: 90000000 adrp x0, 400000 <_init-0x480>
400758: 91362000 add x0, x0, #0xd88 // x0=0x400d88
40075c: 910063a2 add x2, x29, #0x18 // x2=x29+0x18 = 0x7ffffff3b8
400760: aa0003e3 mov x3, x0 // x3=0x400d88
400764: a9400460 ldp x0, x1, [x3] // x0=[0x400d88]=0x200000001, x1=[0x400d90]=0xfffffff700000003
400768: a9000440 stp x0, x1, [x2] // [x29+0x18]=0x200000001, [x28+0x20]=0xfffffff700000003
40076c: a9410460 ldp x0, x1, [x3, #16] // x0=0x500000004 x1=0xfffffff800000006
400770: a9010440 stp x0, x1, [x2, #16] // 0x7ffffff3c8:0x0000000500000004 0x7ffffff3d0:0xfffffff800000006
400774: 910063a0 add x0, x29, #0x18 // x0 = 0x7ffffff3b8
400778: f90033a0 str x0, [x29, #96] // 0x7ffffff400:0x7ffffff3b8
40077c: 52800041 mov w1, #0x2 // w1 = #2
400780: f94037a0 ldr x0, [x29, #104] // x0 = 0x7ffffff3b0
400784: 94000021 bl 400808 <sum> // 400808(0x7ffffff3b0, 2)
400788: b9005fa0 str w0, [x29, #92] // 0x7ffffff3fc:0xfffff3b80000001e
40078c: 52800041 mov w1, #0x2 // #2
400790: f94033a0 ldr x0, [x29, #96] // x0 = 0x7ffffff3b8
400794: 94000035 bl 400868 <sum2d> // 400868(0x7ffffff3b8, 2)
400798: b9005ba0 str w0, [x29, #88]
40079c: 90000000 adrp x0, 400000 <_init-0x480>
4007a0: 9136a000 add x0, x0, #0xda8
4007a4: 9100e3a2 add x2, x29, #0x38
4007a8: aa0003e3 mov x3, x0
4007ac: a9400460 ldp x0, x1, [x3]
4007b0: a9000440 stp x0, x1, [x2]
4007b4: f9400860 ldr x0, [x3, #16]
4007b8: f9000840 str x0, [x2, #16]
4007bc: 9100e3a0 add x0, x29, #0x38
4007c0: 528000c1 mov w1, #0x6 // #6
4007c4: 94000011 bl 400808 <sum>
4007c8: b90057a0 str w0, [x29, #84]
4007cc: 90000000 adrp x0, 400000 <_init-0x480>
4007d0: 91356000 add x0, x0, #0xd58
4007d4: b9405fa1 ldr w1, [x29, #92]
4007d8: 97ffff46 bl 4004f0 <printf@plt>
4007dc: 90000000 adrp x0, 400000 <_init-0x480>
4007e0: 9135a000 add x0, x0, #0xd68
4007e4: b9405ba1 ldr w1, [x29, #88]
4007e8: 97ffff42 bl 4004f0 <printf@plt>
4007ec: 90000000 adrp x0, 400000 <_init-0x480>
4007f0: 9135e000 add x0, x0, #0xd78
4007f4: b94057a1 ldr w1, [x29, #84]
4007f8: 97ffff3e bl 4004f0 <printf@plt>
4007fc: d503201f nop
400800: a8c77bfd ldp x29, x30, [sp], #112
400804: d65f03c0 ret
/*
x29 0x7ffffff3a0 549755810720
x30 0x400788 4196232
sp 0x7ffffff3a0 0x7ffffff3a0
pc 0x400808 0x400808
*/
0000000000400808 <sum>:
400808: d10083ff sub sp, sp, #0x20 // sp = 0x7ffffff380
40080c: f90007e0 str x0, [sp, #8] // x0 = 0x7ffffff3b0
400810: b90007e1 str w1, [sp, #4] // w1 = 2
400814: b9001bff str wzr, [sp, #24] // 0x7ffffff398: 0x0000000000000000
400818: b9001fff str wzr, [sp, #28] // 0x7ffffff39c: 0xfffff41000000000
40081c: 1400000c b 40084c <sum+0x44>
400820: b9801fe0 ldrsw x0, [sp, #28] // x0 = 0 x0 = 1
400824: d37ef400 lsl x0, x0, #2 // x0 = 0 x0 = 4
400828: f94007e1 ldr x1, [sp, #8] // x1 = 0x7ffffff3b0 0x7ffffff3b0
40082c: 8b000020 add x0, x1, x0 // x0 = 0x7ffffff3b0 0x7ffffff3b4
400830: b9400000 ldr w0, [x0] // w0 = 10 w0 = 20
400834: b9401be1 ldr w1, [sp, #24] // w1 = 0 w1 = 10
400838: 0b000020 add w0, w1, w0 // w0 = 10 w0 = 30
40083c: b9001be0 str w0, [sp, #24] // [sp+24]=10 [sp+24]=30
400840: b9401fe0 ldr w0, [sp, #28] // w0 = 0 w0 = 1
400844: 11000400 add w0, w0, #0x1 // w0 = 1 w0 = 2
400848: b9001fe0 str w0, [sp, #28] // [sp+28]=1 [sp+28]=2
40084c: b9401fe1 ldr w1, [sp, #28] // w1 = 0, 1 2
400850: b94007e0 ldr w0, [sp, #4] // w0 = 2 2
400854: 6b00003f cmp w1, w0
400858: 54fffe4b b.lt 400820 <sum+0x18> // b.tstop lt == <
40085c: b9401be0 ldr w0, [sp, #24] // w0 = 30
400860: 910083ff add sp, sp, #0x20 // sp = 0x7ffffff3a0
400864: d65f03c0 ret
/*
x29 0x7ffffff3a0 549755810720
x30 0x400798 4196248
sp 0x7ffffff3a0 0x7ffffff3a0
pc 0x400868 0x400868
*/
0000000000400868 <sum2d>:
400868: d10083ff sub sp, sp, #0x20 // sp = 0x7ffffff380
40086c: f90007e0 str x0, [sp, #8] // 0x7ffffff3b8
400870: b90007e1 str w1, [sp, #4] // 2
400874: b90017ff str wzr, [sp, #20] // 0
400878: b9001fff str wzr, [sp, #28] // 0
40087c: 14000015 b 4008d0 <sum2d+0x68>
400880: b9001bff str wzr, [sp, #24] // 0
400884: 1400000d b 4008b8 <sum2d+0x50>
400888: b9801fe0 ldrsw x0, [sp, #28] // x0 = 0 x0 = 0
40088c: d37cec00 lsl x0, x0, #4 // x0 = 0 x0 = 0
400890: f94007e1 ldr x1, [sp, #8] // x1 = 0x7ffffff3b8 x1=0x7ffffff3b8
400894: 8b000020 add x0, x1, x0 // x0 = 0x7ffffff3b8 x0=0x7ffffff3b8
400898: b9801be1 ldrsw x1, [sp, #24] // x1 = 0 x1 = 1
40089c: b8617800 ldr w0, [x0, x1, lsl #2] // [0x7ffffff3b8]=1 [0x7ffffff3bc]=2
4008a0: b94017e1 ldr w1, [sp, #20] // w1 = 0
4008a4: 0b000020 add w0, w1, w0 // w0 = 1
4008a8: b90017e0 str w0, [sp, #20] // [sp+20]=1
4008ac: b9401be0 ldr w0, [sp, #24] // w0 = 0
4008b0: 11000400 add w0, w0, #0x1 // w0 = 1
4008b4: b9001be0 str w0, [sp, #24] // [sp+24] = 1
4008b8: b9401be0 ldr w0, [sp, #24] // 0, 1
4008bc: 71000c1f cmp w0, #0x3 // [ EL=0 SS N ]
4008c0: 54fffe4d b.le 400888 <sum2d+0x20> // <= j
4008c4: b9401fe0 ldr w0, [sp, #28]
4008c8: 11000400 add w0, w0, #0x1
4008cc: b9001fe0 str w0, [sp, #28]
4008d0: b9401fe1 ldr w1, [sp, #28] // w1 = 0
4008d4: b94007e0 ldr w0, [sp, #4] // w0 = 2
4008d8: 6b00003f cmp w1, w0 // 0x80200000 [ EL=0 SS N ]
4008dc: 54fffd2b b.lt 400880 <sum2d+0x18> // b.tstop
4008e0: b94017e0 ldr w0, [sp, #20]
4008e4: 910083ff add sp, sp, #0x20
4008e8: d65f03c0 ret
/*
x19 0x400c80 4197504
x20 0x0 0
x21 0x400500 4195584
x22 0x0 0
x23 0x0 0
x29 0x7ffffff410 549755810832
x30 0x400c58 4197464
sp 0x7ffffff410 0x7ffffff410
pc 0x4008ec 0x4008ec
cpsr 0x60200000 [ EL=0 SS C Z ]
*/
00000000004008ec <bbb>:
4008ec: a9ba7bfd stp x29, x30, [sp, #-96]!
4008f0: 910003fd mov x29, sp // 0x7ffffff3b0
4008f4: a90153f3 stp x19, x20, [sp, #16]
4008f8: a9025bf5 stp x21, x22, [sp, #32]
4008fc: f9001bf7 str x23, [sp, #48]
400900: 910003f4 mov x20, sp // x20 = 0x7ffffff3b0
400904: aa1403f7 mov x23, x20 // x23 = 0x7ffffff3b0
400908: 52800074 mov w20, #0x3 // #3
40090c: b90053b4 str w20, [x29, #80] // [x29+80]=3
400910: 52800094 mov w20, #0x4 // #4
400914: b90057b4 str w20, [x29, #84] // [x29+84]=4
400918: b94057b4 ldr w20, [x29, #84] // w20=4
40091c: b94053b5 ldr w21, [x29, #80] // w21=3
400920: 93407e96 sxtw x22, w20 // x22=4
400924: d10006d6 sub x22, x22, #0x1 // x22=4-1=3
400928: f9002fb6 str x22, [x29, #88] // [x29+88]=3
40092c: 93407e96 sxtw x22, w20 // x22=4
400930: aa1603f2 mov x18, x22 // x18=4
400934: d2800013 mov x19, #0x0 // #0
400938: d37bfe56 lsr x22, x18, #59 // x22 = 4>>59 = 0x0
40093c: d37bea6d lsl x13, x19, #5 // x13 = 0<<5 = 0x0
400940: aa0d02cd orr x13, x22, x13 // x13 = 0x0|0 = 0x0
400944: d37bea4c lsl x12, x18, #5 // x12 = 4<<5 = 10000000b = 0x80
400948: 93407eac sxtw x12, w21 // x12 = 3
40094c: d100058c sub x12, x12, #0x1 // x12 = 3-1 = 2
400950: f90027ac str x12, [x29, #72] // [x29+72]=2
400954: 93407e8c sxtw x12, w20 // x12 = 4
400958: aa0c03e6 mov x6, x12 // x6 = 4
40095c: d2800007 mov x7, #0x0 // x7 = #0
400960: 93407eac sxtw x12, w21 // x12 = 3
400964: aa0c03e4 mov x4, x12 // x4 = 3
400968: d2800005 mov x5, #0x0 // #0
40096c: 9b047ccd mul x13, x6, x4 // x13 = 4*3 = 12
400970: 9bc47ccc umulh x12, x6, x4 // x12 = 4*3 = 0
400974: 9b0430ec madd x12, x7, x4, x12 // x12 = x12+x7*x4 = 0+0 = 0
400978: 9b0530cc madd x12, x6, x5, x12 // x12 = x12+x6*x5 = 0+4*0=0
40097c: aa0d03f0 mov x16, x13 // x16 = 12
400980: aa0c03f1 mov x17, x12 // x17 = 0
400984: d37bfe04 lsr x4, x16, #59 // x4 = 12>>59 = 0
400988: d37bea2b lsl x11, x17, #5 // x11 = 0 << 5 = 0
40098c: aa0b008b orr x11, x4, x11 // x11 = 0|0 = 0
400990: d37bea0a lsl x10, x16, #5 // x10 = 12<<5 = 0x180
400994: 93407e84 sxtw x4, w20 // x4 = 4
400998: aa0403e2 mov x2, x4 // x2 = 4
40099c: d2800003 mov x3, #0x0 // #0
4009a0: 93407ea4 sxtw x4, w21 // x4 = 3
4009a4: aa0403e0 mov x0, x4 // x0 = 3
4009a8: d2800001 mov x1, #0x0 // #0
4009ac: 9b007c45 mul x5, x2, x0 // x5 = x2*x0 = 4*3 = 12
4009b0: 9bc07c44 umulh x4, x2, x0 // x4 = x2*x0 = 0
4009b4: 9b001064 madd x4, x3, x0, x4 // x4 = x4+x3*x0 = 0+0 = 0
4009b8: 9b011044 madd x4, x2, x1, x4 // x4 = x4+x2*x1 = 0+4*0=0
4009bc: aa0503ee mov x14, x5 // x14 = 12
4009c0: aa0403ef mov x15, x4 // x15 = 0
4009c4: d37bfdc0 lsr x0, x14, #59 // x0 = 12>>59 = 0
4009c8: d37be9e9 lsl x9, x15, #5 // x9 = 0 << 5 = 0
4009cc: aa090009 orr x9, x0, x9 // x9 = 0|0 = 0
4009d0: d37be9c8 lsl x8, x14, #5 // x8 = 12<<5 = 0x180
4009d4: 93407e81 sxtw x1, w20 // x1 = 4
4009d8: 93407ea0 sxtw x0, w21 // x0 = 3
4009dc: 9b007c20 mul x0, x1, x0 // x0 = 12
4009e0: d37ef400 lsl x0, x0, #2 // x0 = 12<<2 = 0x30
4009e4: 91000c00 add x0, x0, #0x3 // x0 = 0x33
4009e8: 91003c00 add x0, x0, #0xf // x0 = 0x42
4009ec: d344fc00 lsr x0, x0, #4 // x0 = 0x42>>4 = 0x4
4009f0: d37cec00 lsl x0, x0, #4 // x0 = 4<<4 = 0x40
4009f4: cb2063ff sub sp, sp, x0 // sp = 0x7ffffff3b0-0x40 = 0x7ffffff370
4009f8: 910003e0 mov x0, sp // x0 = 0x7ffffff370
4009fc: 91000c00 add x0, x0, #0x3 // x0 = 0x7ffffff373
400a00: d342fc00 lsr x0, x0, #2 // x0 = 0x7ffffff373 >> 2 = 0x1ffffffcdc
400a04: d37ef400 lsl x0, x0, #2 // x0 = 0x1ffffffcdc << 2 = 0x7ffffff370
400a08: f90023a0 str x0, [x29, #64] // 0x7ffffff3f0: 0x0000007ffffff370
400a0c: 910002ff mov sp, x23 // sp = 0x7ffffff3b0
400a10: d503201f nop
400a14: 910003bf mov sp, x29 // sp = 0x7ffffff3b0
400a18: a94153f3 ldp x19, x20, [sp, #16]
400a1c: a9425bf5 ldp x21, x22, [sp, #32]
400a20: f9401bf7 ldr x23, [sp, #48]
400a24: a8c67bfd ldp x29, x30, [sp], #96
400a28: d65f03c0 ret
0000000000400a2c <array_cal>:
400a2c: a9bc7bfd stp x29, x30, [sp, #-64]!
400a30: 910003fd mov x29, sp
400a34: 90000000 adrp x0, 400000 <_init-0x480>
400a38: 913a2000 add x0, x0, #0xe88 // x0=0x400e88
400a3c: 9100a3a2 add x2, x29, #0x28 // x2=0x7ffffff3f8
400a40: aa0003e3 mov x3, x0 // x3=0x400e88
400a44: a9400460 ldp x0, x1, [x3] // x0=0x200000001 x1=0x400000003
400a48: a9000440 stp x0, x1, [x2]
400a4c: b9401060 ldr w0, [x3, #16] // w0 = 9
400a50: b9001040 str w0, [x2, #16]
400a54: 9100a3a0 add x0, x29, #0x28 // x0 = 0x7ffffff3f8
400a58: 91005000 add x0, x0, #0x14 // x0 = 0x7ffffff40c
400a5c: f90013a0 str x0, [x29, #32]
400a60: 9100a3a0 add x0, x29, #0x28 // x0 = 0x7ffffff3f8
400a64: 11000400 add w0, w0, #0x1 // w0 = 0xfffff3f9
400a68: 93407c00 sxtw x0, w0 // 0xfffffffffffff3f9
400a6c: f9000fa0 str x0, [x29, #24] // 0x7ffffff3e8: 0xfffffffffffff3f9
400a70: 9100a3a0 add x0, x29, #0x28 // x0 = 0x7ffffff3f8
400a74: 91005000 add x0, x0, #0x14 // x0 = 0x7ffffff40c
400a78: b90017a0 str w0, [x29, #20] // w0 = 0x7ffffff40c 0x7ffffff3e4:0xfffff3f9fffff40
400a7c: 9100a3a1 add x1, x29, #0x28 // x1 = 0x7ffffff3f8 a
400a80: 90000000 adrp x0, 400000 <_init-0x480>
400a84: 91372000 add x0, x0, #0xdc8 // x0 = 0x400dc8
400a88: 97fffe9a bl 4004f0 <printf@plt>
400a8c: 9100a3a1 add x1, x29, #0x28 // x1 = 0x7ffffff3f8 &a
400a90: 90000000 adrp x0, 400000 <_init-0x480>
400a94: 91376000 add x0, x0, #0xdd8 // x0 = 0x400dd8
400a98: 97fffe96 bl 4004f0 <printf@plt>
400a9c: 9100a3a0 add x0, x29, #0x28 // x0 = 0x7ffffff3f8
400aa0: 91001000 add x0, x0, #0x4 // x0 = 0x7ffffff3fc a+1
400aa4: 90000001 adrp x1, 400000 <_init-0x480>
400aa8: 91372022 add x2, x1, #0xdc8 // x2 = 0x400dc8
400aac: aa0003e1 mov x1, x0 // x1 = 0x7ffffff3fc
400ab0: aa0203e0 mov x0, x2 // x0 = 0x400dc8
400ab4: 97fffe8f bl 4004f0 <printf@plt>
400ab8: 9100a3a0 add x0, x29, #0x28
400abc: 91005000 add x0, x0, #0x14 // &a+1
400ac0: 90000001 adrp x1, 400000 <_init-0x480>
400ac4: 91376022 add x2, x1, #0xdd8
400ac8: aa0003e1 mov x1, x0
400acc: aa0203e0 mov x0, x2
400ad0: 97fffe88 bl 4004f0 <printf@plt>
400ad4: b94017a1 ldr w1, [x29, #20] // temp = &a+1
400ad8: 90000000 adrp x0, 400000 <_init-0x480>
400adc: 9137a000 add x0, x0, #0xde8
400ae0: 97fffe84 bl 4004f0 <printf@plt>
400ae4: b94017a1 ldr w1, [x29, #20] // temp = &a+1
400ae8: 90000000 adrp x0, 400000 <_init-0x480>
400aec: 9137e000 add x0, x0, #0xdf8
400af0: 97fffe80 bl 4004f0 <printf@plt>
400af4: 910053a1 add x1, x29, #0x14 // &temp
400af8: 90000000 adrp x0, 400000 <_init-0x480>
400afc: 91382000 add x0, x0, #0xe08
400b00: 97fffe7c bl 4004f0 <printf@plt>
400b04: f94013a0 ldr x0, [x29, #32]
400b08: b9400001 ldr w1, [x0] // *ptr1
400b0c: 90000000 adrp x0, 400000 <_init-0x480>
400b10: 91386000 add x0, x0, #0xe18
400b14: 97fffe77 bl 4004f0 <printf@plt>
400b18: f94013a0 ldr x0, [x29, #32]
400b1c: b9400001 ldr w1, [x0] // *ptr1
400b20: 90000000 adrp x0, 400000 <_init-0x480>
400b24: 9138a000 add x0, x0, #0xe28
400b28: 97fffe72 bl 4004f0 <printf@plt>
400b2c: f94013a1 ldr x1, [x29, #32] // ptr1
400b30: 90000000 adrp x0, 400000 <_init-0x480>
400b34: 9138e000 add x0, x0, #0xe38
400b38: 97fffe6e bl 4004f0 <printf@plt>
400b3c: f94013a1 ldr x1, [x29, #32] // ptr1
400b40: 90000000 adrp x0, 400000 <_init-0x480>
400b44: 9138a000 add x0, x0, #0xe28
400b48: 97fffe6a bl 4004f0 <printf@plt>
400b4c: 910083a1 add x1, x29, #0x20 // &ptr1
400b50: 90000000 adrp x0, 400000 <_init-0x480>
400b54: 91392000 add x0, x0, #0xe48
400b58: 97fffe66 bl 4004f0 <printf@plt>
400b5c: f94013a0 ldr x0, [x29, #32]
400b60: d1001000 sub x0, x0, #0x4 // ptr1[-1]
400b64: b9400001 ldr w1, [x0]
400b68: 90000000 adrp x0, 400000 <_init-0x480>
400b6c: 91396000 add x0, x0, #0xe58
400b70: 97fffe60 bl 4004f0 <printf@plt>
400b74: f9400fa1 ldr x1, [x29, #24] // ptr2
400b78: 90000000 adrp x0, 400000 <_init-0x480>
400b7c: 9139a000 add x0, x0, #0xe68
400b80: 97fffe5c bl 4004f0 <printf@plt>
400b84: 910063a1 add x1, x29, #0x18 // &ptr2
400b88: 90000000 adrp x0, 400000 <_init-0x480>
400b8c: 9139e000 add x0, x0, #0xe78
400b90: 97fffe58 bl 4004f0 <printf@plt>
400b94: 52800000 mov w0, #0x0 // #0
400b98: a8c47bfd ldp x29, x30, [sp], #64
400b9c: d65f03c0 ret
/*
x29 0x7ffffff410 549755810832
x30 0x400c70 4197488
sp 0x7ffffff410 0x7ffffff410
pc 0x400ba0 0x400ba0
*/
0000000000400ba0 <ccc>:
400ba0: a9bc7bfd stp x29, x30, [sp, #-64]!
400ba4: 910003fd mov x29, sp
400ba8: a9017fbf stp xzr, xzr, [x29, #16]
400bac: a9027fbf stp xzr, xzr, [x29, #32]
400bb0: f9001bbf str xzr, [x29, #48]
400bb4: 52800160 mov w0, #0xb // #11
400bb8: b90013a0 str w0, [x29, #16]
400bbc: 528001e0 mov w0, #0xf // #15
400bc0: b90017a0 str w0, [x29, #20]
400bc4: 52800280 mov w0, #0x14 // #20
400bc8: b9001ba0 str w0, [x29, #24]
400bcc: 52800320 mov w0, #0x19 // #25
400bd0: b9001fa0 str w0, [x29, #28]
400bd4: 528003c0 mov w0, #0x1e // #30
400bd8: b90023a0 str w0, [x29, #32]
400bdc: 910043a0 add x0, x29, #0x10
400be0: 91002000 add x0, x0, #0x8
400be4: f9001fa0 str x0, [x29, #56]
400be8: f9401fa0 ldr x0, [x29, #56]
400bec: b9400001 ldr w1, [x0]
400bf0: 90000000 adrp x0, 400000 <_init-0x480>
400bf4: 913a8000 add x0, x0, #0xea0
400bf8: 97fffe3e bl 4004f0 <printf@plt>
400bfc: f9401fa0 ldr x0, [x29, #56]
400c00: d1001000 sub x0, x0, #0x4
400c04: b9400001 ldr w1, [x0]
400c08: 90000000 adrp x0, 400000 <_init-0x480>
400c0c: 913a8000 add x0, x0, #0xea0
400c10: 97fffe38 bl 4004f0 <printf@plt>
400c14: f9401fa0 ldr x0, [x29, #56]
400c18: d1002000 sub x0, x0, #0x8
400c1c: b9400001 ldr w1, [x0]
400c20: 90000000 adrp x0, 400000 <_init-0x480>
400c24: 913a8000 add x0, x0, #0xea0
400c28: 97fffe32 bl 4004f0 <printf@plt>
400c2c: b94037a1 ldr w1, [x29, #52]
400c30: 90000000 adrp x0, 400000 <_init-0x480>
400c34: 913a8000 add x0, x0, #0xea0
400c38: 97fffe2e bl 4004f0 <printf@plt>
400c3c: 52800000 mov w0, #0x0 // #0
400c40: a8c47bfd ldp x29, x30, [sp], #64
400c44: d65f03c0 ret
0000000000400c48 <main>:
400c48: a9bf7bfd stp x29, x30, [sp, #-16]!
400c4c: 910003fd mov x29, sp
400c50: 97fffeb9 bl 400734 <aaa>
400c54: 97ffff26 bl 4008ec <bbb>
400c58: 97fffe69 bl 4005fc <array1>
400c5c: 97fffe89 bl 400680 <array2>
400c60: 97fffe8c bl 400690 <array3>
400c64: 97fffea0 bl 4006e4 <array4>
400c68: 97ffff71 bl 400a2c <array_cal>
400c6c: 97ffffcd bl 400ba0 <ccc>
400c70: 52800000 mov w0, #0x0 // #0
400c74: a8c17bfd ldp x29, x30, [sp], #16
400c78: d65f03c0 ret
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