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module bjqxw(a,b,sum,cout);input a,b;output sum,cout;reg sum,cout;always @(a or b)begincase({a,b})2'b00:beginsum=0;cout=0;end2'b01:beginsum=1;cout=0;end2'b10:beginsum=1;cout=0;end2'b11:beginsum=0;cout=1;end endcaseend
endmodule

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module bjqxwsimu;reg a,b;wire sum,cout;bjqxw sl(a,b,sum,cout);initialbegina=0;b=0;endalways #10 {a,b}={a,b}+1;
endmodule

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module add(a,b,sum,cout);input a,b;output sum,cout;xor(sum,a,b);and(cout,a,b);
endmodule

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module add1;reg a,b;wire sum,cout;add ul(a,b,sum,cout);initialbegina=0;b=0;endalways #10 {a,b}={a,b}+1;
endmodule

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endmodulemodule add3(a,b,sum,cout);input a,b;output sum,cout;wire sum,cout;assign sum=a^b;assign cout=a&b;
endmodule

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module add1;reg ain,bin;reg clk;wire sum1,cout1;initialbeginain=0;bin=0;clk=0;endalways #50 clk=~clk;always @(posedge clk)beginain={$random}%2;#3 bin={$random}%2;endadd3 ul(.a(ain),.b(bin),.sum(sum1),.cout(cout1));
endmodule

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module qjq(a,b,cin,sum,cout);input a,b,cin;output sum,cout;reg sum,cout;always @(a or b or cin)begincase ({cin,a,b})3'b000:beginsum=0;cout=0;end3'b001:beginsum=1;cout=0;end3'b010:beginsum=1;cout=0;end3'b011:beginsum=0;cout=1;end3'b100:beginsum=1;cout=0;end3'b101:beginsum=0;cout=1;end3'b110:beginsum=0;cout=1;end3'b111:beginsum=1;cout=1;endendcase end
endmodule

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module qjq1;reg a,b,cin;wire sum,cout;qjq ul(a,b,cin,sum,cout);initialbegina=0;b=0;cin=0;endalways #10 {a,b,cin}={a,b,cin}+1;
endmodule

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module qiq(a,b,cin,sum,cout);input a,b,cin;output sum,cout;wire q1,q2,q3;xor(sum,a,b,cin);or(q1,a,b);or(q2,b,cin);or(q3,a,cin);and(cout,q1,q2,q3);
endmodule

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module qjq1;reg a,b,cin;wire sum,cout;qiq ul(a,b,cin,sum,cout);initialbegina=0;b=0;cin=0;endalways #10 {a,b,cin}={a,b,cin}+1;
endmodule

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module qjq(a,b,cin,sum,cout);input a,b,cin;output sum,cout;assign {sum,cout}=a+b+cin;
endmodule

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module qjqsimu;reg a,b,cin;wire sum,cout;qjq sl(a,b,cin,sum,cout);initialbegina=0;b=0;cin=a&b;endalways #20 {a,b}={a,b}+1;
endmodule

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module qjq(a,b,cin,sum,cout);input [3:0] a,b;input cin;output [3:0] sum;output cout;assign {sum,cout}=a+b+cin;
endmodule

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module qjqsimu;reg [3:0] a,b;reg cin;wire [3:0] sum;wire cout;qjq sl(a,b,cin,sum,cout);initialbegina=4'b0000;b=4'b0000;cin=0;endalways #20 {a,b}={a,b}+4'b0001;
endmodule