Microcontrollers and Embedded Systems

Part 8: I/O Communication Protocol

$I^{_{2}}C$ (Inter-Integrated Circuit 内置集成电路): a multi-master, multi-slave, single-ended, serial computer bus.

For attaching low-speed peripherals (外围设备) to computer motherboards and embedded systems.

Characteristics: open-drain(open collector)

Protocol(协议): Serial, Half Duplex

SMBus:A subset of $I^{_{2}}C$ but the protocols are defined more strictly.

Purpose: promote robustness and interoperability(互用性)

Modern $I^{_{2}}C$ systems incorporate policies and rules from SMBus.

$I^{_{2}}C$ architecture:uses only two bidirectional open-drain lines: Serial Data Line (SDA) and Serial Clock Line (SCL), pulled up with resistors.

Typical voltages used are +5 V or +3.3 V, although systems with other voltages are permitted

The I²C reference designs:

address space: 7-bit or 10-bit (depending on the device used).
speeds:
- standard mode (100 Kbit/s) and low-speed mode (10 kbit/s); but arbitrarily low clock frequencies are also allowed.
- Recent revisions of I²C can host more nodes and run at faster speeds: fast mode (400 kbit/s), fast mode plus or Fm+ (1 Mbit/s), and high-speed mode (3.4 Mbit/s). These speeds are more widely used on embedded systems than on PCs.
There are also other features, such as 16-bit addressing.

问题：address space 和 addressing关系是什么？

The reference design is a bus with a clock (SCL) and data (SDA) lines with 7-bit (or 10-bit) addressing. The bus has two roles for nodes:
- Master node — a node that generates the clock (SCL) and initiates communication with slaves
- a node that receives the clock and responds when addressed by the master
I2C is a multi-master bus, i.e., any number of master nodes can be present.
The master and slave roles may be changed between messages (after a STOP is sent)
Four potential modes of operation for a given bus device, although most devices only use a single role (master/slave):
- master transmit — master node is sending data to a slave
- master receive — master node is receiving data from a slave
- slave transmit — slave node is sending data to the master
- slave receive — slave node is receiving data from the master

General Timing diagram

Start: Data transfer is initiated with a START bit (S) that is signaled by SDA being pulled low while SCL stays high

Data transition: SDA sets the 1st data bit level while keeping SCL low (during the blue-bar time.)

Data sampling: The data is sampled (received) when SCL rises (green) for the first bit (B1)

This process repeats: SDA transitioning while SCL is low, and the data being read(receive) while SCL is high (B2, …, BN)

Stop: A STOP bit (P) is signaled when SDA is pulled high while SCL is high

Master-Node Read/Write

The I2C’s start and stop signals are different from the start bits and stop bits used in asynchronous serial communication, which are distinguished from data bits only by their timing

The master is initially in master transmit mode by sending (i) a START; then (ii) the 7-bit address of the slave it wishes to communicate with; and then (iii) a single bit representing whether it wishes to transmit (0: write) or receive (1: read)

If the addressed slave exists on the bus, it will respond with an ACK bit (active low for acknowledged) for that address. The master then continues in either transmit or receive mode (according to the read/write bit it sent), and the slave continues in the complementary mode (receive or transmit, respectively)

The address and the data bytes are sent most significant bit first

STM32F103’s $I^{_{2}}C$

I2C bus Interface:

serves as an interface between the microcontroller and the serial I2C bus
provides Multimaster capability, and controls all I2C bus-specific sequencing, protocol, arbitration, and timing
supports the standard mode (Sm; up to 100 kHz) and Fm mode (Fm; up to 400 kHz)

It is used for a variety of purposes:

CRC generation and verification, SMBus (system management bus), and PMBus (power management bus)

Depending on specific device implementation, DMA capability may be available for reducing CPU overload

$I^{_{2}}C$ Message protocols（协议）

The basic transaction（交易） begins with a START and ends with a STOP

Single message where a master writes data to a slave
Single message where a master reads data from a slave
Combined format, where a master issues at least two reads or writes to one or more slaves

In a combined transaction

Each read or write begins with a START and the slave address.
The START conditions after the first one are also called repeated START bits.
Repeated STARTs are not preceded(先于) by STOP conditions, which is how slaves know that the next message is part of the same transaction.

STM32F103 use two-level data registers (data register + data shift register).

SMBus introduction

a two-wire interface that is based on I2C principles of operation.

Provides a control bus for system and power management related tasks.

Designed for communication with low-bandwidth (低带宽) devices on a motherboard（母板）, especially power-related chips such as:

a laptop's rechargeable battery subsystem
sensors for temperature, fan, or voltage; and
lid switches (限位开关) and clock chips

A system may use SMBus to pass messages to and from devices instead of toggling individual control lines.

SMBus types

The System Management Bus Specification refers to three types of devices:

Slave: a device that is receiving or responding to a command.
Master: a device that issues commands, generates the clocks, and terminates the transfer
Host: a specialized master (特殊master) that provides the main interface to the system's CPU

A host must be a master-slave and must support the SMBus host notify(通知) protocol.

Only one host is allowed in a system.

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