欢迎FPGA工程师加入官方微信技术群

点击蓝字关注我们FPGA之家-中国最好最大的FPGA纯工程师社群

本实验基于xilinx ARTIX-7芯片验证实现，有时间有兴趣的朋友可在其他FPGA芯片上实现验证。
当大家看到《xilinx verilog语法技巧(三)–RAM的初始化》文章的时候很多人认为initial语句，$readmemb语句均是不可综合语句(只能用来写测试文件)，但是xilinx的综合器已经悄然改变了这一点。
rams_init_file源码：

// Initializing Block RAM from external data file// Binary data// File: rams_init_file.v

module rams_init_file (clk, we, addr, din, dout);input clk;input we;input [5:0] addr;input [31:0] din;output [31:0] dout;

reg [31:0] ram [0:63];reg [31:0] dout;

initial begin$readmemb("rams_init_file.data",ram);end

always @(posedge clk)beginif (we)     ram[addr] <= din;  dout <= ram[addr];end endmodule

rams_init_file.data源文件：

00001110110000011001111011000110001010110010110101010010001000110111010001010001100001110000111101000001010000100101001110010100000010011010011111111010001010110010110100101111111010101010011111101111000100111000111101101101100011110100100110010000111011110000000110001110001111001001111111011111001110101011111001001010111001110101001111101100110010101100010000100110110011110010100110001011100101011111111111100001111101011101100100000101101110100100101100000011100101011010111011100001111111001010111010011110011011110110100101000011011100010101010001101111100001100010010011110000111101101111001100001011101011010011110101001001000111000101110000101011111110111010111001011101000100100111010010110101111101110001000001010111011011011110011111000111101010110000110101110100000011101111111000011111000100111101011110001110010111010110111000111110001101010110111110111100000000010011101011011011110000010011010011011111000100000001111111001011011001111101010101100100100000011100100101110000100010000001001110110010100011111100100010001110100101000110000110000000100111010011100111100011110111110100101000101010100001111000000011011110100011111011101110110011010111101111000110011001000101111000010010101101110111001001110010111010111101101011001101010011101101010001110110011010011110110111000101010001010000011000100000011001011011100110101011101000001101010000111001010110111000111111000001111101011101010100101000000000111111110110111100100011000011001000000010001111100110001110101100010010111001001111111111101111010100010100011111000011000101000011100110100000011011010010111110101000111010011000011110110010100111001101011111010110100100101110110010100100010011111110011011010111110010111101100100110111011000010011011110110110110111100101110011100110100111001110010000101111110101100000000000101101111100101011001010100110011010000010001000011011110010101111110010011100011101010010000110001000011100010100100000111100101111110001101101111010110000100010100000000101001000011100000100011000110100010100111010010011010100010001100100100111

tb_rams_init_file测试顶层文件：

`timescale 1ns / 1psmodule tb_rams_init_file(       input clk,       input reset,       output [2:0] led_rgb0,       output [2:0] led_rgb1,       output [2:0] led_rgb2,       output [2:0] led_rgb3);reg [5:0] addr;wire  [31:0] dout;reg [27:0] cnt;

assign led_rgb0 = dout[2:0];assign led_rgb1 = dout[5:3];assign led_rgb2 = dout[8:6];assign led_rgb3 = dout[11:9];

always @(posedge clk ) beginif(reset==1'b1) begin    cnt   <= 28'd0;    addr <= 0;  endelse if(cnt == 28'd100000000)begin//1s    cnt <= 28'd0;    addr <= addr +1;  endelse begin    cnt   <= cnt + 1;    addr <= addr;  endendrams_init_file u_rams_init_file(.clk(clk), .we(1'b0), .addr(addr), .din(32'b0), .dout(dout));endmodule

约束文件(根据自己板卡)：

set_property PACKAGE_PIN E3 [get_ports clk]set_property IOSTANDARD LVCMOS33 [get_ports clk]

set_property PACKAGE_PIN D9 [get_ports reset]set_property IOSTANDARD LVCMOS33 [get_ports reset]

set_property PACKAGE_PIN E1 [get_ports led_rgb0[0]]set_property IOSTANDARD LVCMOS33 [get_ports led_rgb0[0]]

set_property PACKAGE_PIN G6 [get_ports led_rgb0[1]]set_property IOSTANDARD LVCMOS33 [get_ports led_rgb0[1]]

set_property PACKAGE_PIN F6 [get_ports led_rgb0[2]]set_property IOSTANDARD LVCMOS33 [get_ports led_rgb0[2]]

set_property PACKAGE_PIN G4 [get_ports led_rgb1[0]]set_property IOSTANDARD LVCMOS33 [get_ports led_rgb1[0]]

set_property PACKAGE_PIN G3 [get_ports led_rgb1[1]]set_property IOSTANDARD LVCMOS33 [get_ports led_rgb1[1]]

set_property PACKAGE_PIN J4 [get_ports led_rgb1[2]]set_property IOSTANDARD LVCMOS33 [get_ports led_rgb1[2]]

set_property PACKAGE_PIN H4 [get_ports led_rgb2[0]]set_property IOSTANDARD LVCMOS33 [get_ports led_rgb2[0]]

set_property PACKAGE_PIN J3 [get_ports led_rgb2[1]]set_property IOSTANDARD LVCMOS33 [get_ports led_rgb2[1]]

set_property PACKAGE_PIN J2 [get_ports led_rgb2[2]]set_property IOSTANDARD LVCMOS33 [get_ports led_rgb2[2]]

set_property PACKAGE_PIN K2 [get_ports led_rgb3[0]]set_property IOSTANDARD LVCMOS33 [get_ports led_rgb3[0]]

set_property PACKAGE_PIN K1 [get_ports led_rgb3[1]]set_property IOSTANDARD LVCMOS33 [get_ports led_rgb3[1]]

set_property PACKAGE_PIN H6 [get_ports led_rgb3[2]]set_property IOSTANDARD LVCMOS33 [get_ports led_rgb3[2]]

测试效果：

视频结果展示

欢迎通信工程师和FPGA工程师关注公众号

全国第一大FPGA微信技术群

欢迎大家加入全国FPGA微信技术群，这个群体拥有数万工程师、一群热爱技术的工程师，这里的FPGA工程师相互帮助，相互分享，技术氛围浓厚！赶紧叫上小伙伴一起加入吧！！

用手指按住就可以加入FPGA全国技术群哦

FPGA之家元器件芯城

优势元器件服务，有需求请扫码联系群主：金娟 邮箱：293580331@qq.com 欢迎推荐给采购

ACTEL、AD部分优势订货(经营全系列)：

XILINX、ALTERA优势现货或订货(经营全系列)：

(以上器件为部分型号，更多型号请咨询群主金娟)

服务理念：FPGA之家元器件自营芯城，旨在方便工程师快速方便购买器件服务，经过数年竭诚服务，我们的客服遍布国内大型上市公司、军工科研单位、中小企业、最大的优势是强调服务至上的理念、并且做到快速交货、价格优惠！

直营品牌：Xilinx ALTERA ADI TI NXP ST E2V、镁光 等百余元器件品牌，尤其擅长欧美对华禁运器件，欢迎工程师朋友把我们推荐给采购或者亲自咨询我们！我们将一如既往提供业内最佳服务！

FPGA技术群官方鸣谢品牌：Xilinx、 intel(Altera)、microsemi(，Actel)、LattIC e，Vantis，Quicklogic，Lucent等