Slow to Fast Clock Domains？

Let us examine the setup and hold checks when a path goes from a slower clock domain to a faster clock domain. This is shown in Figure 8-22.

时钟定义：

 create_clock -name CLKM -period 20 -waveform {0 10} [get_ports CLKM]create_clock -name CLKP -period 5 -waveform {0 2.5} [get_ports CLKP]

When the clock frequencies are different for the launch flip-flop and the capture flip-flop, STA is performed by first determining a common base period. An example of a message produced when STA is performed on such a design with the above two clocks is given below. The faster clock is expanded so that a common period is obtained.

Figure 8-23 shows the setup check. **By default**, the most constraining setup edge relationship is used, which in this case is the very next capture edge. Here is a setup path report that shows this.

Notice that the launch clock is at time 0ns while the capture clock is at time 5ns. As discussed earlier, hold checks are related to the setup checks and ensure that the data launched by a clock edge does not interfere with the previous capture. Here is the hold check timing report.

In the above example, we can see that the launch data is available every fourth cycle of the capture clock. Let us assume that the intention is not to capture data on the very next active edge of CLKP, but to capture on every 4th capture edge. This assumption gives the combinational logic between the flip-flops four periods of CLKP to propagate, which is 20ns. We can do this by setting the following multicycle specification:

set_multicycle_path 4 -setup -from [get_clocks CLKM] -to [get_clocks CLKP] -end

The -end specifies that the multicycle of 4 refers to the end point or the capture clock. This multicycle specification changes the setup and hold checks to the ones shown in Figure 8-24. Here is the setup report.

Figure 8-24 shows the hold check - note that the hold check is derived from the setup check and defaults to one cycle preceding the intended capture edge. Here is the hold timing report. Notice that the hold capture edge is at 15ns, one cycle prior to the setup capture edge.

In most designs, this is not the intended check, and the hold check should be moved all the way back to where the launch edge is. We do this by setting a hold multicycle specification of 3.

set_multicycle_path 3 -hold -from [get_clocks CLKM] -to [get_clocks CLKP] -end

The cycle of 3 moves the hold checking edge back three cycles, that is, to time 0ns. The distinction with a setup multicycle is that in setup, the setup capture edge moves forward by the specified number of cycles from the default setup capture edge; in a hold multicycle, the hold check edge moves backward from the default hold check edge (one cycle before setup edge). The -end option implies that we want to move the endpoint (or capture edge) back by the specified number of cycles, which is that of the capture clock. Instead of -end, the other choice, the -start option, specifies the number of launch clock cycles to move by; the -end option specifies the number of capture clock cycles to move by. The -end is the default for a multicycle setup and the -start is the default for multicycle hold.

总结

1.首先判断是

快时钟采慢时钟
找出这两个时钟的最大公约数，n ( The faster clock is
expanded so that a common period is obtained.)

设置：

set_multicycle_path n -setup -from [get_clocks CLKM] -to [get_clocks CLKP] -end
set_multicycle_path n -hold -from [get_clocks CLKM] -to [get_clocks CLKP] -end

2.In summary, if a setup multicycle of N cycles is specified, then most likely a hold multicycle of N-1 cycles should also be specified. A good rule of thumb for multi-frequency multicycle path specification in the case of paths between slow to fast clock domains is to use the -end option. With this option, the setup and hold checks are adjusted based upon the clock*
**

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STA圣经之: Slow to Fast Clock Domains

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Slow to Fast Clock Domains？

总结

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