VDHL VGA控制器设计实现显示器屏幕保护模块

基本功能：

1、通过FPGA板的VGA接口在显示器上分别显示不同颜色的横向、竖直条纹图案，横向条纹和竖直条纹的切换通过FPGA板上的按键实现。

2、通过VGA控制器，在屏幕上显示640*480的单色背景，并在该背景上叠加一个小方块，该小方块能够在屏幕上上下左右移动，实现屏幕保护的效果。

3、VGA单色的背景色自定，小方块的大小自定；

4、该小方块能够按照一定的轨迹在屏幕上运行，速度适中。

大三下学期的实验，贴出代码仅供参考：

1、分频模块：

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity fenpin is

port

(

clk_fp_in :in std_logic;

reset_fp :in std_logic;

clk_fp_out :out std_logic;

clk_fp_dis :out std_logic

);

end fenpin;

architecture Behavioral of fenpin is

signal clk_signal :std_logic;

signal clk_dis :std_logic;

signal cnt:integer range 999999 downto 0 :=0;--移动

begin

process(clk_fp_in,reset_fp)

begin

if(reset_fp='1')then

clk_signal<= '0';

elsif(clk_fp_in'eventand clk_fp_in = '1')then

if(clk_signal= '0')then

clk_signal<= '1';

else

clk_signal<= '0';

endif;

endprocess;

clk_fp_out<= clk_signal;

process(clk_fp_in,reset_fp)

begin

if(reset_fp='1')then

cnt<= 0;

clk_dis<= '0';

elsif(clk_fp_in'eventand clk_fp_in = '1')then

if(cnt< 499999)then

cnt<= cnt+1;

clk_dis<= '1';

elsif(cnt= 999999)then

cnt<= 0;

else

cnt<= cnt+1;

clk_dis<= '0';

endif;

endprocess;

clk_fp_dis<= clk_dis;

end Behavioral;

2、VGA控制模块：

library IEEE;

useIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

entity sync is

port( clk_sync :instd_logic;

reset_sync :in std_logic;

V_sync :out std_logic;

H_sync :out std_logic;

Ready_sync :out std_logic;

Lie_Add_sync :out integer range 800 downto 0;

Hang_Add_sync :out integer range 525 downto 0

);

end sync;

architectureBehavioral of sync is

signal count_h:integer range 800 downto 0;

signal count_v:integer range 525 downto 0;

signal isReady :std_logic;

begin

process (clk_sync,reset_sync)

begin

if(reset_sync='1')then

count_h <= 0;

H_sync <= '0';

elsif(clk_sync'event and clk_sync='1')then

if(count_h=799)then

count_h <= 0;

else

count_h <=count_h + 1;

if(count_h <96)then

H_sync <= '0';

else

H_sync <= '1';

end if;

end process;

process (clk_sync,reset_sync)

begin

if(reset_sync='1')then

count_v <= 0;

V_sync <= '0';

elsif(clk_sync'event and clk_sync='1')then

if(count_v = 524)then

count_v <= 0;

elsif(count_h=799)then

count_v <=count_v + 1;

else

if(count_v <3)then

V_sync <='0';

else

V_sync <='1';

end if;

end process;

process (reset_sync,clk_sync)

begin

if(reset_sync='1')then

isReady <= '0';

Lie_Add_sync <= 0;

Hang_Add_sync<= 0;

elsif(clk_sync'event and clk_sync='1')then

if((count_h >144)and(count_h < 785)and(count_v > 34)and(count_v < 515))then

isReady <= '1';

Lie_Add_sync <=count_h - 145;

Hang_Add_sync<=count_v - 35;

else

isReady <= '0';

Lie_Add_sync <=0;

Hang_Add_sync<=0;

end if;

end process;

Ready_sync <= isReady;

end Behavioral;

3、VGA显示模块：

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_ARITH.ALL;

entityvga_control is

port( clk_vga :instd_logic;

signal_dis :in std_logic;

reset_vga :in std_logic;

choose_vga :in std_logic;

Ready_vga :in std_logic;

Lie_Add_vga :in integer range 800 downto 0; --0~640

Hang_Add_vga:in integer range 525downto 0; --0~480

rom_add :out std_logic_vector (13 downto 0);

rom_data :in std_logic_vector (7 downto 0);

RGB_vga_out :out std_logic_vector (7 downto 0);

RGB_vga_in :in std_logic_vector (7 downto 0)

);

end vga_control;

architectureBehavioral of vga_control is

type state is(s0,s1,s2,s3);--状态机类型

signalcurrent:state;

signal x:integerrange 639 downto 0 :=100;--移动

signal y:integerrange 479 downto 0 :=100;--移动

signalx_signal:std_logic;

signaly_signal:std_logic;

signal move :std_logic;

begin

process(choose_vga,reset_vga)

begin

if(reset_vga ='1')then

current <=s0;

elsif(choose_vga'event andchoose_vga ='0')then--检测到下降沿才开始响应

case current is

when s0 =>

current <=s1;

when s1 =>

current <=s2;

when s2 =>

current <=s3;

when s3 =>

current <=s0;

when others =>

current <=s0;

end case;

end if;

end process;

process (clk_vga,reset_vga)

begin

if(reset_vga='1')then

RGB_vga_out <="00000000";

move <='1';

elsif(clk_vga'event and clk_vga ='1')then

if(Ready_vga='1')then --可以显示

case current is

when s0=>--竖条纹

caseLie_Add_vga is --0~640

when0 to 79 =>RGB_vga_out <= "11100000";--红，蓝，绿，蓝，红，绿，红，蓝

when 80 to 159 =>RGB_vga_out <= "00000011";

when160 to 239 => RGB_vga_out <="00011100";

when240 to 319 => RGB_vga_out <="00000011";

when320 to 399 => RGB_vga_out <="11100000";

when400 to 479 => RGB_vga_out <="00011100";

when480 to 559 => RGB_vga_out <="11100000";

when560 to 639 => RGB_vga_out <="00000011";

whenothers => RGB_vga_out<= "00000000";

endcase;

when s1=>--横条纹

caseHang_Add_vga is --0~480

when0 to 59 =>RGB_vga_out <= "11100000";--红，蓝，绿，蓝，红，绿，红，蓝

when60 to 119 => RGB_vga_out <= "00000011";

when120 to 179 => RGB_vga_out <="00011100";

when180 to 239 => RGB_vga_out <="00000011";

when240 to 299 => RGB_vga_out <="11100000";

when300 to 359 => RGB_vga_out <="00011100";

when360 to 419 => RGB_vga_out <="11100000";

when420 to 479 => RGB_vga_out <="00000011";

whenothers => RGB_vga_out<= "00000000";

endcase;

when s2=>--调色观察

if(Hang_Add_vga> y and Hang_Add_vga< 128+y and Lie_Add_vga>x andLie_Add_vga < 128+x )then

move <='0';

RGB_vga_out<= RGB_vga_in;

else

move <='1';

RGB_vga_out<= "00000000";

endif;

when s3=>--屏保

if(Hang_Add_vga>y and Hang_Add_vga< 128+y and Lie_Add_vga>x and Lie_Add_vga <128+x)then

move <='0';

rom_add<= conv_std_logic_vector((Hang_Add_vga-y)*128 + Lie_Add_vga-x,14);

RGB_vga_out<= rom_data;

else

move <='1';--使用这个信号只是为了让扫描完一次再移动，但由于背景跟图片颜色不一样，还是有拖影，所以，这个信号可以不用！

RGB_vga_out<= "00000000";

endif;

when others=>

RGB_vga_out<= "00000000";

end case;

end if;

end process;

--屏保图片的移动实现

process(reset_vga,signal_dis)

begin

if(reset_vga='1')then

x_signal <='1';

x <=0;

elsif(signal_dis'event andsignal_dis ='1')then

if(move='1')then

if(x_signal ='1')then

if(x<634-128)then

x<= x+1;

else

x<= x-1;

x_signal<='0';

end if;

else

if(x<1)then

x<= x+1;

x_signal<='1';

else

x<= x-1;

end if;

end process;

process(reset_vga,signal_dis)

begin

if(reset_vga='1')then

y_signal <='1';

y <=0;

elsif(signal_dis'event andsignal_dis ='1')then

if(move='1')then

if(y_signal ='1')then

if(y<479-128)then

y<= y+1;

else

y<= y-1;

y_signal<='0';

end if;

else

if(y<1)then

y<= y+1;

y_signal<='1';

else

y<= y-1;

end if;

end process;

end Behavioral;

5、顶层模块：

library IEEE;

useIEEE.STD_LOGIC_1164.ALL;

entity VGA_top is

port( clk :instd_logic; --50M时钟输入

reset :in std_logic; --复位，高有效

choose :in std_logic;

--pll_led :out std_logic; --提示PLL正常工作的LED

V :outstd_logic;

H :outstd_logic;

RGB :out std_logic_vector (7 downto 0);

RGB_top :in std_logic_vector (7 downto 0)

);

end VGA_top;

architectureBehavioral of VGA_top is

component fenpin

port( clk_fp_in : in std_logic;

reset_fp :in std_logic;

clk_fp_out :out std_logic;

clk_fp_dis :out std_logic

);

end component;

component sync

port( clk_sync :instd_logic;

reset_sync :in std_logic;

V_sync :out std_logic;

H_sync :out std_logic;

Ready_sync :out std_logic;

Lie_Add_sync :out integer range 800 downto 0;

Hang_Add_sync :out integer range 525 downto 0

);

end component;

component vga_control

port( clk_vga :instd_logic;

signal_dis :in std_logic;

reset_vga :in std_logic;

choose_vga :in std_logic;

Ready_vga :in std_logic;

Lie_Add_vga :in integer range 800 downto 0; --0~640

Hang_Add_vga:ininteger range 525 downto 0; --0~480

rom_add :out std_logic_vector (13 downto 0);

rom_data :in std_logic_vector (7 downto 0);

RGB_vga_out :out std_logic_vector (7 downto 0);

RGB_vga_in :in std_logic_vector (7 downto 0)

);

end component;

COMPONENT rom1

PORT (

clka : IN STD_LOGIC;

addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);

douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

);

END COMPONENT;

signal clk_sig :std_logic;

signal clk_dis :std_logic;

signal Ready :std_logic;

signal Lie_Add :integer range 800 downto0; --0~640

signal Hang_Add:integer range 525 downto0; --0~480

signal rom_add_signal:STD_LOGIC_VECTOR(13 DOWNTO 0);

signal rom_data_signal:STD_LOGIC_VECTOR(7DOWNTO 0);

begin

u1:fenpin

port map( clk,

reset,

clk_sig,

clk_dis

);

u2:sync

port map( clk_sig,

reset,

Ready,

Lie_Add,

Hang_Add

);

u3:vga_control

port map( clk_sig,

clk_dis,

reset,

choose,

Ready,

Lie_Add,

Hang_Add,

rom_add_signal,

rom_data_signal,

RGB,

RGB_top

);

u4:rom1

PORT map( clk_sig,

rom_add_signal,

rom_data_signal

);

end Behavioral;

FPGA开发板截图：

VDHL VGA控制器设计实现显示器屏幕保护模块相关推荐

基于FPGA的大屏幕全彩LED扫描控制器设计
关键字:FPGA 大屏幕 LED 1 引言作为大型平板显示设备的一种,LED 显示屏以其使用寿命长.维护费用低.功耗低等特点在显示领域占有重要的位置.特别在近年,带有红.绿.蓝三基色以及灰度显示效果 ...
嵌入式平台的VGA接口设计及VGA接口时序波形图
大多数嵌入式产品的显示终端都选择LCD,但在某些需要大屏幕显示的应用中,工业级LCD的价格比较昂贵,且现有的大屏幕显示器(包括CRT显示器和LCD显示器)一般都采用统一的15针VGA显示接口.三星公司 ...
windows xp 屏幕保护程序_小礼物：3D Windows XP 屏幕保护程序
航通社旗下公众号"56K小猫"(微信:modem56k),原创文章未经授权禁止转载.航通社微信:lifeissohappy 微博:@航通社生 / 活 / 小 / 妙 / 招从昨 ...
华为网络计算机关闭屏幕保护,华为手机的屏幕保护太烦人了怎样才能关闭它
KIA1999的回答华为手机的屏幕保护关闭方法如下: 1.首先打开手机,来到手机桌面,找到[设置]菜单,直接[点击]进入设置 2.进入设置菜单后,往下滑动屏幕找到"通知和状态栏" ...
液晶显示器不宜使用屏幕保护程序
在使用台式电脑时,很多人都喜欢使用屏幕保护程序,当他们转为使用笔记本电脑时,这个好习惯也被保留了下来,但他们却不知屏幕保护程序对笔记本电脑非但没有任何好处,反而还会造成一些负面影响. 实际上屏 ...
计算机无法屏保,电脑屏幕保护程序为什么不能修改原因及解决方法【详细介绍】...
为何不能修改电脑屏幕保护程序? 虽然屏幕保护并不是专门为省电而设计的,但一般Windows下的屏幕保护程序都比较暗,大幅度降低屏幕亮度,有一定的省电作用. 现行显示器分为两种--CRT显示器和LCD显 ...
html网页屏保,屏幕保护是什么
屏幕保护是为了保护显示器而设计的一种专门的程序.屏幕保护有三个作用,分别是:1.保护显像管:2.保护个人隐私:3.省电. 本文操作环境:windows10系统.thinkpad t490电脑. 屏幕保 ...
[译]用C#创建一个屏幕保护程序
用C#创建一个屏幕保护程序原文地址: http://www.harding.edu/fmccown/screensaver/screensaver.html 简介一个Windows屏幕保护程序是根 ...
使用Win32 SDK开发屏幕保护程序
暮鼓集行走集 1.引言屏幕保护程序(Screen Saver)的历史几乎与视窗操作系统的历史一样悠久,设计它的目的是为了保护CRT显示器使其的使用寿命更长.但随着技术的进步,新型的CRT显示 ...

VDHL VGA控制器设计实现显示器屏幕保护模块

VDHL VGA控制器设计实现显示器屏幕保护模块相关推荐

最新文章

热门文章