一、Uart串口：

1. 串行通信：占用引脚少，但速度慢。

1. 异步通信：不带有时钟同步信号，通过波特率限定通信。

1. 全双工：可同时进行双向通信。

二、Uart通信数据格式（一般不使用停止位）

三、时序图

四、信号介绍

五、代码展示

// data width = 8module uart_rx#(parameter FREQ = 50    ,//clock frequency  MHzparameter BPS  = 115200 //baud rate)(clk     ,//input, clockrst_n   ,//input, reset active in lowrxd     ,//input, receive datadat_vld ,//output, data validdat_o    //output, output data );input               clk     ;input               rst_n   ;input               rxd     ;output  reg         dat_vld ;output  reg [7:0]   dat_o   ;localparam CLK_CNT_MAX = FREQ*1000000 / BPS - 1;localparam CCM_BIT = $clog2(CLK_CNT_MAX);reg [1:0]           rxd_r           ;reg [CCM_BIT-1:0]   clk_cnt         ;reg                 rx_flag         ;reg [3:0]           rx_cnt          ;//0-9(data:1-8)//get the down edge of the input data(rxd) always@(posedge clk or negedge rst_n) beginif (!rst_n)rxd_r <= 2'b00;elserxd_r <= {rxd_r[0],rxd};endwire dn_edge = (!rxd_r[0]) & rxd_r[1];//down edge of the rxd//division of the clkalways@(posedge clk or negedge rst_n) beginif (!rst_n)clk_cnt <= 'b0;else if (rx_flag)clk_cnt <= (clk_cnt == CLK_CNT_MAX)? 'b0 : (clk_cnt + 1'b1);elseclk_cnt <= 'b0;end//rx_flagalways@(posedge clk or negedge rst_n) beginif (!rst_n)rx_flag <= 1'b0;else if (dn_edge)rx_flag <= 1'b1;else if ((rx_cnt == 4'd9) && (clk_cnt == CLK_CNT_MAX/2))rx_flag <= 1'b0;elserx_flag <= rx_flag;end//rx_cntalways@(posedge clk or negedge rst_n) beginif (!rst_n)rx_cnt <= 'b0;else if (rx_flag)rx_cnt <= (clk_cnt == CLK_CNT_MAX)? (rx_cnt + 1'b1) : rx_cnt;elserx_cnt <= 'b0;end//dat_vldalways@(posedge clk or negedge rst_n) beginif (!rst_n)dat_vld <= 1'b0;else if ((rx_cnt == 4'd8) && (clk_cnt == CLK_CNT_MAX))dat_vld <= 1'b1;elsedat_vld <= 1'b0;end//dat_oalways@(posedge clk or negedge rst_n) beginif (!rst_n)dat_o <= 'b0;else if(rx_flag) beginif (clk_cnt == CLK_CNT_MAX/2)case(rx_cnt)4'd1 : dat_o[0] <= rxd_r[1];       4'd2 : dat_o[1] <= rxd_r[1];4'd3 : dat_o[2] <= rxd_r[1];4'd4 : dat_o[3] <= rxd_r[1];4'd5 : dat_o[4] <= rxd_r[1];4'd6 : dat_o[5] <= rxd_r[1];4'd7 : dat_o[6] <= rxd_r[1];4'd8 : dat_o[7] <= rxd_r[1];default: dat_o <= dat_o;endcaseelsedat_o <= dat_o;endelsedat_o <= dat_o;endendmodule

六、结果测试

使用上位机串口调试助手发送一个数据，将这个数据显示到FPGA开发板上面的led数码管显示。

需要添加两个代码：

1、8位的二进制数据转换为12位的BCD码。

2、BCD码显示在FPGA开发板上面的代码。

module bin2BCD(bin ,    bcd);input   [7:0]   bin;output  [11:0]  bcd;reg [3:0] hundreds  ;reg [3:0] tens      ;reg [3:0] ones      ; integer i;always@(*) beginhundreds = 4'b0000;tens     = 4'b0000;ones     = 4'b0000;for(i=7;i>=0;i=i-1) beginif(hundreds >= 5) hundreds = hundreds + 2'b11;if(tens >= 5) tens = tens + 2'b11;if(ones >= 5) ones = ones + 2'b11;hundreds = hundreds << 1;hundreds[0] = tens[3];tens = tens << 1;tens[0] = ones[3];ones = ones << 1;ones[0] = bin[i];endendassign bcd = {hundreds,tens,ones};endmodule

//FPGA board have the six display led: seg_scn
//default:not display the dot,just number: seg_led[7]=1module BCD_led_disp#(parameter CLK_FREQ  = 50,  // the frequency the clock MHzparameter DISP_INTV = 100,//the switch interval of the led, usparameter LED_NUM   = 3     //the number of the LED used)(clk     , rst_n   ,bcd_vld ,bcd     ,seg_scn ,seg_led );input                       clk     ;input                       rst_n   ;input                       bcd_vld ;//input, data_bcd enable 1 clockinput       [4*LED_NUM-1:0] bcd     ;output  reg [5:0]           seg_scn ;output      [7:0]           seg_led ;localparam CNTSCN_MAX = DISP_INTV * 100 / 20 - 1;reg [$clog2(CNTSCN_MAX)-1:0] cnt_scn;reg [4*LED_NUM-1:0] bcd_r;assign seg_led[7] = 1'b1; always@(posedge clk or negedge rst_n) beginif (!rst_n)cnt_scn <= 'b0;else if (bcd_vld || (cnt_scn == CNTSCN_MAX))cnt_scn <= 'b0;elsecnt_scn <= cnt_scn + 1'b1;endalways@(posedge clk or negedge rst_n) beginif (!rst_n)seg_scn <= 6'b111111;else if (bcd_vld)seg_scn <= 6'b111110;else if (cnt_scn == CNTSCN_MAX)seg_scn <= {seg_scn[5:(6-LED_NUM)],seg_scn[LED_NUM-2:0],seg_scn[LED_NUM-1]};endalways@(posedge clk or negedge rst_n) beginif (!rst_n)bcd_r <= 'b0;else if (bcd_vld)bcd_r <= bcd;else if (cnt_scn == CNTSCN_MAX)bcd_r <= {bcd_r[3:0],bcd_r[LED_NUM*4-1:4]};endwire [3:0] bcdnum_temp = bcd_r[3:0];led_disp u_led_disp(.num     (bcdnum_temp),.led     (seg_led[6:0]));endmodulemodule led_disp(num     ,led    );input       [3:0]   num ;output  reg [6:0]   led ;always@(*) begincase(num)4'b0000: led = 7'b1000000;4'b0001: led = 7'b1111001;4'b0010: led = 7'b0100100;4'b0011: led = 7'b0110000;4'b0100: led = 7'b0011001;4'b0101: led = 7'b0010010;4'b0110: led = 7'b0000010;4'b0111: led = 7'b1111000;4'b1000: led = 7'b0000000;4'b1001: led = 7'b0010000;4'b1010: led = 7'b0001000;4'b1011: led = 7'b0000011;4'b1100: led = 7'b1000110;4'b1101: led = 7'b0100001;4'b1110: led = 7'b0000110;4'b1111: led = 7'b0001110;default: led = 7'b1111111;endcaseend
endmodule

测试时需要将三个代码例化到一个top里面:

module top(clk     ,  rst_n   ,rxd     ,seg_scn ,seg_led );input           clk     ;input           rst_n   ;input           rxd     ;output  [5:0]   seg_scn ;output  [7:0]   seg_led ;wire            dat_vld ;wire    [7:0]   dat_o   ;wire    [11:0]  bcd     ;assign txd = 1;uart_rx#(.FREQ(50),.BPS(115200)//baud rate)u_uart_rx(.clk     (clk    ),.rst_n   (rst_n  ),.rxd     (rxd    ),//input, receive data.dat_vld (dat_vld),//output, data valid.dat_o   (dat_o  ) //output, output data );bin2BCD u_bin2BCD(.bin (dat_o),    .bcd (bcd));BCD_led_disp#(.CLK_FREQ  (50 ),  // the frequency the clock MHz.DISP_INTV (100),//the switch interval of the led, us.LED_NUM   (3  )  //the number of the LED used)(.clk     (clk    ), .rst_n   (rst_n  ),.bcd_vld (dat_vld),.bcd     (bcd    ),.seg_scn (seg_scn),.seg_led (seg_led));endmodule

七、测试结果展示