用Verilog实现Conway‘s Game of Life 16x16(HDLbits的Conwaylife题)

Title:Conwaylife

Conway’s Game of Life is a two-dimensional cellular automaton.

The “game” is played on a two-dimensional grid of cells, where each cell is either 1 (alive) or 0 (dead). At each time step, each cell changes state depending on how many neighbours it has:

0-1 neighbour: Cell becomes 0.
2 neighbours: Cell state does not change.
3 neighbours: Cell becomes 1.
4+ neighbours: Cell becomes 0.

The game is formulated for an infinite grid. In this circuit, we will use a 16x16 grid. To make things more interesting, we will use a 16x16 toroid, where the sides wrap around to the other side of the grid. For example, the corner cell (0,0) has 8 neighbours: (15,1), (15,0), (15,15), (0,1), (0,15), (1,1), (1,0), and (1,15). The 16x16 grid is represented by a length 256 vector, where each row of 16 cells is represented by a sub-vector: q[15:0] is row 0, q[31:16] is row 1, etc. (This tool accepts SystemVerilog, so you may use 2D vectors if you wish.)

load: Loads data into q at the next clock edge, for loading initial state.
q: The 16x16 current state of the game, updated every clock cycle.
The game state should advance by one timestep every clock cycle.

题目为康威的生命游戏

其实总的大体是个D触发器,只不过这个D是“二维”的，题目中用一维256位宽数据代替16x16二维数据，下一个状态由上一个状态转变而来，而“二维”数据的边界为环形（既被填充），具体填充规则如下图所示（下图蓝色框中为原始数据，周围既为填充数）：

每个元素的下一个状态都由当前状态的邻域1的个数所决定，如下图所示，（0，0）的邻域有8个，当这其中8个含1的有0~1个时：Q* = 0; 有2个时：Q* = Q; 有三个时：Q* = 1; 有4个及以上时：Q* = 0。

//模块定义
Module Declaration
module top_module(
input clk,
input load,
input [255:0] data,
output [255:0] q
);

废话不多少，直接上代码

module top_module(input clk,input load,input [255:0] data,output reg [255:0] q
); wire  [15:0] d [15:0];wire  [17:0] d_loop [17:0];//extend qassign d_loop[0][17:0] = {q[240],q[255:240],q[255]};assign d_loop[17][17:0] = {q[0],q[15:0],q[15]};genvar m;generate for(m=0;m<16;m=m+1)begin:loopd_loop_extend u_d_loop_extend({q[(16*m)],q[(16*m+15):(16*m)],q[(16*m+15)]},d_loop[(m+1)][17:0]);endendgenerate //next q stategenvar i,j;generatefor(i=1;i<17;i=i+1)begin:loop0for(j=1;j<17;j=j+1)begin:loop1neighbor_num u_neighbor_num({d_loop[i-1][j-1],d_loop[i-1][j],d_loop[i-1][j+1],d_loop[i][j-1],d_loop[i][j+1],d_loop[i+1][j-1],d_loop[i+1][j],d_loop[i+1][j+1]},d_loop[i][j],d[i-1][j-1]);endendendgenerate  always@(posedge clk)if(load)q <= data;elseq <= {d[15][15:0],d[14][15:0],d[13][15:0],d[12][15:0],d[11][15:0],d[10][15:0],d[9][15:0],d[8][15:0],d[7][15:0],d[6][15:0],d[5][15:0],d[4][15:0],d[3][15:0],d[2][15:0],d[1][15:0],d[0][15:0]};endmodulemodule d_loop_extend(   //供generate模块调用填充数据邻域input    [17:0] data_in  ,output [17:0]  data_out
);assign data_out = data_in;
endmodulemodule neighbor_num(  //计算领域中1的个数input [7:0]  nums,input          d0    ,output  reg q0
);
wire [3:0] num;
assign num = nums[0]+nums[1]+nums[2]+nums[3]+nums[4]+nums[5]+nums[6]+nums[7];always@(*)case(num)4'd2:q0 = d0;4'd3: q0 = 1'b1;default: q0 = 1'b0;endcase
endmodule

仿真图：