【FPGA】【Verilog】【基础模块】状态机
2024-05-07 22:24:22
结果：
module seq(ans,clk,reset,x,in);input clk,reset,x,in;output ans;reg [3:0] state;reg ans;parameter IDLE='d0;parameter A='d1;parameter B='d2;parameter C='d3;parameter D ='d4;parameter E ='d5;always @(posedge clk)if(!reset)begin state <= IDLE;endelse casex(state)IDLE : if (in == 1)begin state <= A;endelsestate <= IDLE;A: if (x == 1)begin state <= B;endB: if (x == 1)begin state <= C;endelse state <= A;C: if (x == 1)begin state <= D;endelse state <= A;D: if (x == 1)begin state <= E;endelse state <= A;E: if (x == 1)begin ans <= 1'b1;enddefault: state = IDLE;endcase endmodule Testbench:
当数据包含连续的4个以上的1时：
`timescale 1 ns / 1 ns
`include"C:/**********/seq.v"module seqdet_Top;reg clk,rst;reg [15:0] data;wire ans;wire x,in;reg ans_out;assign x = data[15];assign in = 1;always #10 clk = ~clk;always @(posedge clk)data = {data[14:0],data[15]};initial begin clk = 0;rst = 1;#50 rst = 0;#50 rst = 1;data = 'b1_00111_11011_00100;#1000 $stop;endseq m(.ans(ans),.clk(clk),.reset(rst),.x(x),.in(in));always @(posedge clk)case(ans)1: ans_out <= 1;default: ans_out <= 0;endcase endmodule 仿真波形:
当数据不包含连续的4个以上的1时：
`timescale 1 ns / 1 ns
`include"C:/**********/seq.v"module seqdet_Top;reg clk,rst;reg [15:0] data;wire ans;wire x,in;reg ans_out;assign x = data[15];assign in = 1;always #10 clk = ~clk;always @(posedge clk)data = {data[14:0],data[15]};initial begin clk = 0;rst = 1;#50 rst = 0;#50 rst = 1;data = 'b1_10110_11011_00100;#1000 $stop;endseq m(.ans(ans),.clk(clk),.reset(rst),.x(x),.in(in));always @(posedge clk)case(ans)1: ans_out <= 1;default: ans_out <= 0;endcase endmodule 仿真波形：
简化的EPROM的数据写入过程：
module seqrom(rst,clk ,address,data, sda,acknowledge,link_write,main_state,slave_state,slave_state_buffer,finish);input rst,clk;input [7:0] address, data;output sda, acknowledge;output link_write;output [3:0]main_state;output [4:0] slave_state;output [7:0] slave_state_buffer;output finish;reg link_write;reg [3:0] main_state;reg [4:0] slave_state;reg [7:0] slave_state_buffer;reg finish;reg acknowledge;parameter idle = 0,address_write = 1,data_write = 2, stop_acknowledge = 3;parameter bit1 = 1,bit2 = 2,bit3 = 3,bit4 = 4,bit5 = 5,bit6 = 6,bit7 = 7,bit8 = 8;assign sda = link_write ? slave_state_buffer : 1'bz;//当开始写数据时，buffer里的数据就传给sda，没开始写数据时，sda就保持高阻态。always @(posedge clk)begin if(!rst)begin link_write = 0;main_state <= idle;slave_state <= idle;finish <= 0;acknowledge <= 0;slave_state_buffer <= 0;endelse case(main_state)idle: begin link_write <= 0;finish <= 0;acknowledge<= 0;main_state <= address_write;slave_state_buffer <= address;slave_state<= idle;endaddress_write:beginif(finish == 0)begin Buffer_to_ROM;endelse beginfinish <=0;main_state <= data_write;slave_state_buffer <= data;slave_state <= idle;endenddata_write:beginif(finish == 0)begin Buffer_to_ROM;endelse begin link_write <= 0;finish <= 0;main_state <= stop_acknowledge;acknowledge<= 1; endendstop_acknowledge:begin acknowledge <= 0;main_state <= idle;endendcase endtask Buffer_to_ROM;begincase(slave_state)idle: beginlink_write <= 1;slave_state<= bit1;endbit1: beginlink_write <= 1;slave_state_buffer <= slave_state_buffer << 1;slave_state<= bit2;endbit2: beginlink_write <= 1;slave_state_buffer <= slave_state_buffer << 1;slave_state<= bit3;endbit3: beginlink_write <= 1;slave_state_buffer <= slave_state_buffer << 1;slave_state<= bit4;endbit4: beginlink_write <= 1;slave_state_buffer <= slave_state_buffer << 1;slave_state<= bit5;endbit5: beginlink_write <= 1;slave_state_buffer <= slave_state_buffer << 1;slave_state<= bit6;endbit6: beginlink_write <= 1;slave_state_buffer <= slave_state_buffer << 1;slave_state<= bit7;endbit7: beginlink_write <= 1;slave_state_buffer <= slave_state_buffer << 1;slave_state<= bit8;end bit8: beginlink_write <= 0;finish <= 1;end endcase endendtask
endmodule
Testbench:
`timescale 1ns/100ps
`define clk_cycle 50
module writingTop;reg reset,clk;reg[7:0] data,address;wire ack,sda;wire link_write;wire [3:0]main_state;wire [4:0] slave_state;wire [7:0] slave_state_buffer;wire finish;always #`clk_cycle clk = ~clk;initialbeginclk=0;reset=1;data=0;address=0;#(20*`clk_cycle) reset=0;#(20*`clk_cycle) reset=1;#(5000*`clk_cycle) $stop;endalways @(posedge ack) //接收到应答信号后，给出下一个处理对象。begindata=data+1;address=address+1;endseqrom seqrom(.rst(reset),.clk(clk),.data(data),.address(address),.acknowledge(ack),.sda(sda),.link_write(link_write),.main_state(main_state),.slave_state(slave_state),.slave_state_buffer(slave_state_buffer),.finish(finish));
endmodule练习：
module traffic(clk,en,lampAL,lampAG,lampAY,lampAR,lampBL,lampBG,lampBY,lampBR,Acount,Bcount);input clk,en;output reg lampAL,lampAG,lampAY,lampAR,lampBL,lampBG,lampBY,lampBR;output reg [7:0] Acount,Bcount ;wire [7:0] Gcounter ,Ycounter,Lcounter,Rcounter;assign Rcounter = Ycounter + Ycounter + Gcounter + Lcounter;assign Gcounter = 8'd2;assign Ycounter = 8'd1;assign Lcounter = 8'd1;reg [3:0] state;reg [7:0] lamp_counter;reg [32:0] subcounter; wire div_clk;always @(posedge clk)if (!en)subcounter <= 0;else subcounter <= subcounter + 1;always@(posedge subcounter[4] or negedge en)if (!en)begin{lampAL,lampAG,lampAY,lampAR} <= 4'b0010;{lampBL,lampBG,lampBY,lampBR} <= 4'b0010;lamp_counter <= 0;state <= 4'b0;end else case (state)4'd0: //待机状态，全黄begin{lampAL,lampAG,lampAY,lampAR} <= 4'b0010;{lampBL,lampBG,lampBY,lampBR} <= 4'b0010;state <= 4'd1;lamp_counter <= 0;end //--------------A--------------//4'd1: //A的绿灯beginif(lamp_counter == Gcounter)beginstate <= 4'd2;lamp_counter <= 0;end else begin{lampAL,lampAG,lampAY,lampAR} <= 4'b0100;{lampBL,lampBG,lampBY,lampBR} <= 4'b0001;lamp_counter <= lamp_counter + 1'b1;state <= 4'd1;endend4'd2: //A的黄灯begin if(lamp_counter == Ycounter)beginstate <= 4'd3;lamp_counter <= 0;endelse begin{lampAL,lampAG,lampAY,lampAR} <= 4'b0010;{lampBL,lampBG,lampBY,lampBR} <= 4'b0001;lamp_counter <= lamp_counter + 1'b1;state <= 4'd2;end end 4'd3: //A的左转灯begin if(lamp_counter == Lcounter)beginstate <= 4'd4;lamp_counter <= 0;endelse begin{lampAL,lampAG,lampAY,lampAR} <= 4'b1000;{lampBL,lampBG,lampBY,lampBR} <= 4'b0001;lamp_counter <= lamp_counter + 1'b1;state <=4'd3;end end 4'd4: //A的黄灯begin if(lamp_counter == Ycounter)beginstate <= 4'd5;lamp_counter <= 0;endelse begin{lampAL,lampAG,lampAY,lampAR} <= 4'b0010;{lampBL,lampBG,lampBY,lampBR} <= 4'b0001;lamp_counter <= lamp_counter + 1'b1;state <= 4'd4;end end //--------------B--------------// 4'd5: //B的绿灯begin if(lamp_counter == Gcounter)beginstate <= 4'd6;lamp_counter <= 0;end else begin{lampAL,lampAG,lampAY,lampAR} <= 4'b0001;{lampBL,lampBG,lampBY,lampBR} <= 4'b0100;lamp_counter <= lamp_counter + 1'b1;state <= 4'd5;end end 4'd6: //B的黄灯begin if(lamp_counter == Ycounter)beginstate <= 4'd7;lamp_counter <= 0;end else begin{lampAL,lampAG,lampAY,lampAR} <= 4'b0001;{lampBL,lampBG,lampBY,lampBR} <= 4'b0010;lamp_counter <= lamp_counter + 1'b1;state <= 4'd6;end end 4'd7: //B的左转灯begin if(lamp_counter == Lcounter)beginstate <= 4'd8;lamp_counter <= 0;end else begin{lampAL,lampAG,lampAY,lampAR} <= 4'b0001;{lampBL,lampBG,lampBY,lampBR} <= 4'b1000;lamp_counter <= lamp_counter + 1'b1;state <= 4'd7;endend 4'd8: //B的黄灯beginif(lamp_counter == Ycounter)beginstate <= 4'd1;lamp_counter <= 0;endelse begin{lampAL,lampAG,lampAY,lampAR} <= 4'b0001;{lampBL,lampBG,lampBY,lampBR} <= 4'b0010;lamp_counter <= lamp_counter + 1'b1;state <= 4'd8;end end endcase
endmodule testbench:
`timescale 1 ns/ 1 ps
module traffic_vlg_tst();
// constants
// general purpose registers
// test vector input registers
reg clk;
reg en;
// wires
wire [7:0] Acount;
wire [7:0] Bcount;
wire lampAG;
wire lampAL;
wire lampAR;
wire lampAY;
wire lampBG;
wire lampBL;
wire lampBR;
wire lampBY;// assign statements (if any)
traffic i1 (
// port map - connection between master ports and signals/registers .Acount(Acount),.Bcount(Bcount),.clk(clk),.en(en),.lampAG(lampAG),.lampAL(lampAL),.lampAR(lampAR),.lampAY(lampAY),.lampBG(lampBG),.lampBL(lampBL),.lampBR(lampBR),.lampBY(lampBY)
);
initial
begin #100 clk = 0;#500 en = 1;#500 en = 0;#500 en = 1;#5_00_00000 $stop;
end
always #10 clk <= ~clk;
endmodule两种状态机：
moore型： 摩尔 型 状态 机 的 输出 只 与 当前 的 状态 有关。
always@( posedge clk, posedge rst) begin if( rst== 1'b1)state <= 2'b00; else begin case( state)2'b00: begin if( in== 1) state <= 2'b01;else state <= 2'b10; end 2'b01: begin if( in== 1) state <= 2' b11; else state <= 2' b10; end 2'b10: beginif( in== 1)state <= 2'b01else state <= 2'b11; end 2'b11: begin if( in== 1) state <= 2'b01; else state <= 2'b10; endendcase end end always@( posedge clk, posedge rst)begin if( rst== 1'b1) out <= 0;else if( state== 2'b11) out <= 1; else out <= 0; end最终输出（ out） 只在" state== 2' b11" 时 才会 有 输出， 与 输入（ in） 没有 直接 的 关系。
Mealy型：输出 除了 与 当前 的 状态 有关 之外， 还 与 输入 有关。
always@( posedge clk, posedge rst) if( rst== 1' b1) begin state <= 2'b00; out <= 0;end else begin case( state) 2'b00: begin if( in== 1) begin state <= 2'b01; out <= 0; end else begin state <= 2'b10; out <= 0; end end 2'b01: begin if( in== 1) beginstate <= 2'b00; out <= 1;end else begin state <= 2'b10; out <= 0; end end 2'b10: begin if( in== 1) begin state <= 2'b01; out <= 0; end else begin state <= 2'b00; out <= 1; end end default: beginstate <= 2'b00; out <= 0; end endcase end输出（ out） 的 取值 不仅 与 当前 的 状态（ state） 有关， 而且 与 输入（ in） 也 直接 相关。
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