BIOS_CXL_INIT_FLOW
2024-06-22 07:13:44
文章目录
- CXL 初始化 BIOS 打印
- BIOS源码解析 Initialize CXL
- CXL Memory Map BIOS 打印
- BIOS源码解析 Memory Map
CXL 初始化 BIOS 打印
******* Initialize CXL - START *******CXL: IIO EarlyLink Init Start.
HcxType[0] = HCA
[IIO](VMD) [0] VMD disabled for RPs init.
Program HW_INIT using SB access
Program HW_INIT using SB access
Program HW_INIT using SB access
Program HW_INIT using SB access
Program HW_INIT using SB access
Program HW_INIT using SB access
Program HW_INIT using SB access
Program HW_INIT using SB access
Program HW_INIT using SB access
[0] Cpxsmb enabled
MS2IOSF_BANK_DECODER_INIT_START
MS2IOSF BankDecoder: TableSize 119, Recipe Revision 1.16
Hiding DSA Psf1DsaConfig: 0
Hiding DSA Psf1DsaConfig: 0
Hiding DSA Psf1DsaConfig: 0
Hiding DSA Psf1DsaConfig: 0
Hiding DSA Psf1DsaConfig: 100
...
MS2IOSF_BANK_DECODER_INIT_END
[0 p0] DMI device is enabled
[0.1 p1] 00:15:01.0: PCI device 8086:352A is enabled
[0.1 p2] 00:15:02.0: PCI device FFFF:FFFF is disabled (not present)
[0.1 p3] 00:15:03.0: PCI device FFFF:FFFF is disabled (not present)
[0.1 p4] 00:15:04.0: PCI device FFFF:FFFF is disabled (not present)
[0.1 p5] 00:15:05.0: PCI device FFFF:FFFF is disabled (not present)
[0.1 p6] 00:15:06.0: PCI device FFFF:FFFF is disabled (not present)
[0.1 p7] 00:15:07.0: PCI device FFFF:FFFF is disabled (not present)
[0.1 p8] 00:15:08.0: PCI device FFFF:FFFF is disabled (not present)
[0.2 p9] 00:26:01.0: PCI device 8086:352A is enabled
[0.2 p10] 00:26:02.0: PCI device FFFF:FFFF is disabled (not present)
[0.2 p11] 00:26:03.0: PCI device FFFF:FFFF is disabled (not present)
[0.2 p12] 00:26:04.0: PCI device FFFF:FFFF is disabled (not present)
[0.2 p13] 00:26:05.0: PCI device FFFF:FFFF is disabled (not present)
[0.2 p14] 00:26:06.0: PCI device FFFF:FFFF is disabled (not present)
[0.2 p15] 00:26:07.0: PCI device FFFF:FFFF is disabled (not present)
[0.2 p16] 00:26:08.0: PCI device FFFF:FFFF is disabled (not present)
[0.3 p17] 00:37:01.0: PCI device 8086:352A is enabled
[0.3 p18] 00:37:02.0: PCI device FFFF:FFFF is disabled (not present)
[0.3 p19] 00:37:03.0: PCI device FFFF:FFFF is disabled (not present)
[0.3 p20] 00:37:04.0: PCI device FFFF:FFFF is disabled (not present)
[0.3 p21] 00:37:05.0: PCI device FFFF:FFFF is disabled (not present)
[0.3 p22] 00:37:06.0: PCI device FFFF:FFFF is disabled (not present)
[0.3 p23] 00:37:07.0: PCI device FFFF:FFFF is disabled (not present)
[0.3 p24] 00:37:08.0: PCI device FFFF:FFFF is disabled (not present)
[0.4 p25] 00:48:01.0: PCI device 8086:352A is enabled
[0.4 p26] 00:48:02.0: PCI device FFFF:FFFF is disabled (not present)
[0.4 p27] 00:48:03.0: PCI device 8086:352B is enabled
[0.4 p28] 00:48:04.0: PCI device FFFF:FFFF is disabled (not present)
[0.4 p29] 00:48:05.0: PCI device 8086:352C is enabled
[0.4 p30] 00:48:06.0: PCI device FFFF:FFFF is disabled (not present)
[0.4 p31] 00:48:07.0: PCI device 8086:352D is enabled
[0.4 p32] 00:48:08.0: PCI device FFFF:FFFF is disabled (not present)
[0.5 p33] 00:59:01.0: PCI device 8086:352A is enabled
[0.5 p34] 00:59:02.0: PCI device FFFF:FFFF is disabled (not present)
[0.5 p35] 00:59:03.0: PCI device 8086:352B is enabled
[0.5 p36] 00:59:04.0: PCI device FFFF:FFFF is disabled (not present)
[0.5 p37] 00:59:05.0: PCI device 8086:352C is enabled
[0.5 p38] 00:59:06.0: PCI device FFFF:FFFF is disabled (not present)
[0.5 p39] 00:59:07.0: PCI device 8086:352D is enabled
[0.5 p40] 00:59:08.0: PCI device FFFF:FFFF is disabled (not present)
WARNING: Platform does not support uplink port!
HcxType[1] = HCA
[IIO](VMD) [1] VMD disabled for RPs init.
Program HW_INIT using SB access
Program HW_INIT using SB access
Program HW_INIT using SB access
Program HW_INIT using SB access
Program HW_INIT using SB access
Program HW_INIT using SB access
Program HW_INIT using SB access
Program HW_INIT using SB access
Program HW_INIT using SB access
Program HW_INIT using SB access
[1] Cpxsmb enabled
MS2IOSF_BANK_DECODER_INIT_START
MS2IOSF BankDecoder: TableSize 119, Recipe Revision 1.16
Hiding DSA Psf1DsaConfig: 0
Hiding DSA Psf1DsaConfig: 0
Hiding DSA Psf1DsaConfig: 0
Hiding DSA Psf1DsaConfig: 0
Hiding DSA Psf1DsaConfig: 100
Hiding DSA Psf1DsaConfig: 0
。。。
MS2IOSF_BANK_DECODER_INIT_END
[1.1 p1] 00:97:01.0: PCI device 8086:352A is enabled
[1.1 p2] 00:97:02.0: PCI device FFFF:FFFF is disabled (not present)
[1.1 p3] 00:97:03.0: PCI device FFFF:FFFF is disabled (not present)
[1.1 p4] 00:97:04.0: PCI device FFFF:FFFF is disabled (not present)
[1.1 p5] 00:97:05.0: PCI device FFFF:FFFF is disabled (not present)
[1.1 p6] 00:97:06.0: PCI device FFFF:FFFF is disabled (not present)
[1.1 p7] 00:97:07.0: PCI device FFFF:FFFF is disabled (not present)
[1.1 p8] 00:97:08.0: PCI device FFFF:FFFF is disabled (not present)
[1.2 p9] 00:A7:01.0: PCI device 8086:352A is enabled
[1.2 p10] 00:A7:02.0: PCI device FFFF:FFFF is disabled (not present)
[1.2 p11] 00:A7:03.0: PCI device FFFF:FFFF is disabled (not present)
[1.2 p12] 00:A7:04.0: PCI device FFFF:FFFF is disabled (not present)
[1.2 p13] 00:A7:05.0: PCI device FFFF:FFFF is disabled (not present)
[1.2 p14] 00:A7:06.0: PCI device FFFF:FFFF is disabled (not present)
[1.2 p15] 00:A7:07.0: PCI device FFFF:FFFF is disabled (not present)
[1.2 p16] 00:A7:08.0: PCI device FFFF:FFFF is disabled (not present)
[1.3 p17] 00:B7:01.0: PCI device 8086:352A is enabled
[1.3 p18] 00:B7:02.0: PCI device FFFF:FFFF is disabled (not present)
[1.3 p19] 00:B7:03.0: PCI device FFFF:FFFF is disabled (not present)
[1.3 p20] 00:B7:04.0: PCI device FFFF:FFFF is disabled (not present)
[1.3 p21] 00:B7:05.0: PCI device FFFF:FFFF is disabled (not present)
[1.3 p22] 00:B7:06.0: PCI device FFFF:FFFF is disabled (not present)
[1.3 p23] 00:B7:07.0: PCI device FFFF:FFFF is disabled (not present)
[1.3 p24] 00:B7:08.0: PCI device FFFF:FFFF is disabled (not present)
[1.4 p25] 00:C7:01.0: PCI device 8086:352A is enabled
[1.4 p26] 00:C7:02.0: PCI device FFFF:FFFF is disabled (not present)
[1.4 p27] 00:C7:03.0: PCI device 8086:352B is enabled
[1.4 p28] 00:C7:04.0: PCI device FFFF:FFFF is disabled (not present)
[1.4 p29] 00:C7:05.0: PCI device 8086:352C is enabled
[1.4 p30] 00:C7:06.0: PCI device FFFF:FFFF is disabled (not present)
[1.4 p31] 00:C7:07.0: PCI device 8086:352D is enabled
[1.4 p32] 00:C7:08.0: PCI device FFFF:FFFF is disabled (not present)
[1.5 p33] 00:D7:01.0: PCI device 8086:352A is enabled
[1.5 p34] 00:D7:02.0: PCI device FFFF:FFFF is disabled (not present)
[1.5 p35] 00:D7:03.0: PCI device 8086:352B is enabled
[1.5 p36] 00:D7:04.0: PCI device FFFF:FFFF is disabled (not present)
[1.5 p37] 00:D7:05.0: PCI device 8086:352C is enabled
[1.5 p38] 00:D7:06.0: PCI device FFFF:FFFF is disabled (not present)
[1.5 p39] 00:D7:07.0: PCI device 8086:352D is enabled
[1.5 p40] 00:D7:08.0: PCI device FFFF:FFFF is disabled (not present)
[1.6 p41] 00:80:01.0: PCI device 8086:352A is enabled
[1.6 p42] 00:80:02.0: PCI device FFFF:FFFF is disabled (not present)
[1.6 p43] 00:80:03.0: PCI device FFFF:FFFF is disabled (not present)
[1.6 p44] 00:80:04.0: PCI device FFFF:FFFF is disabled (not present)
[1.6 p45] 00:80:05.0: PCI device 8086:352C is enabled
[1.6 p46] 00:80:06.0: PCI device FFFF:FFFF is disabled (not present)
[1.6 p47] 00:80:07.0: PCI device FFFF:FFFF is disabled (not present)
[1.6 p48] 00:80:08.0: PCI device FFFF:FFFF is disabled (not present)
Calling IioEarlyIntiazeEntry Start
[0] IioAllocateMmioResource: Seg=0, MaxStackPerSocket=12[0.0] Temp BUS: 0x00 -> 0x00 | MMIOL: 0x90122000 -> 0x957FFFFF[0.1] Temp BUS: 0x15 -> 0x15 | MMIOL: 0x95900000 -> 0x9F7FFFFF[0.2] Temp BUS: 0x26 -> 0x26 | MMIOL: 0x9F900000 -> 0xA93FFFFF[0.3] Temp BUS: 0x37 -> 0x37 | MMIOL: 0xA9500000 -> 0xB2FFFFFF[0.4] Temp BUS: 0x48 -> 0x48 | MMIOL: 0xB3100000 -> 0xBCBFFFFF[0.5] Temp BUS: 0x59 -> 0x59 | MMIOL: 0xBCD00000 -> 0xC67FFFFF[0.8] Temp BUS: 0x6A -> 0x6A | MMIOL: 0xC6900000 -> 0xC6FFFFFF[0.9] Temp BUS: 0x6F -> 0x6F | MMIOL: 0xC7100000 -> 0xC77FFFFF[0.10] Temp BUS: 0x74 -> 0x74 | MMIOL: 0xC7900000 -> 0xC7FFFFFF[0.11] Temp BUS: 0x79 -> 0x79 | MMIOL: 0xC8100000 -> 0xC87FFFFF
[0] IIO Early Link Training Starting...
Recipy decompressing...
Socket[0] Stack[0] Program RX recipe values START...
Program recipe revision 2.009 (Info : 1.5:, len 2556)
[0] Program RX recipe values END
Recipy decompressing...
Socket[0] Stack[1] Program RX recipe values START...
Program recipe revision 2.009 (Info : 1.5:, len 2966)
[0] Program RX recipe values END
Socket[0] Stack[2] Program RX recipe values START...
Program recipe revision 2.009 (Info : 1.5:, len 2966)
[0] Program RX recipe values END
Socket[0] Stack[3] Program RX recipe values START...
Program recipe revision 2.009 (Info : 1.5:, len 2966)
[0] Program RX recipe values END
Socket[0] Stack[4] Program RX recipe values START...
Program recipe revision 2.009 (Info : 1.5:, len 2966)
[0] Program RX recipe values END
Socket[0] Stack[5] Program RX recipe values START...
Program recipe revision 2.009 (Info : 1.5:, len 2966)
[0] Program RX recipe values END
CXL_IO_PRE_TRAIN_INIT_START
CXL_IO_PRE_TRAIN_INIT_END
FBLP_PRE_TRAIN_INIT_START
FBLP_PRE_TRAIN_INIT_END
[0 p0] IioDmiLinkInit
[0 p0] DMI link speed vector IIO 0xF, PCH 0x7 -> target speed 3
[0] IIO Early Link Training Completed!
[1] IioAllocateMmioResource: Seg=0, MaxStackPerSocket=12[1.1] Temp BUS: 0x97 -> 0x97 | MMIOL: 0xD1500000 -> 0xD97FFFFF[1.2] Temp BUS: 0xA7 -> 0xA7 | MMIOL: 0xD9900000 -> 0xE17FFFFF[1.3] Temp BUS: 0xB7 -> 0xB7 | MMIOL: 0xE1900000 -> 0xE97FFFFF[1.4] Temp BUS: 0xC7 -> 0xC7 | MMIOL: 0xE9900000 -> 0xF17FFFFF[1.5] Temp BUS: 0xD7 -> 0xD7 | MMIOL: 0xF1900000 -> 0xF97FFFFF[1.6] Temp BUS: 0x80 -> 0x80 | MMIOL: 0xC9100000 -> 0xD13FFFFF[1.8] Temp BUS: 0xE7 -> 0xE7 | MMIOL: 0xF9900000 -> 0xF9FFFFFF[1.9] Temp BUS: 0xEC -> 0xEC | MMIOL: 0xFA100000 -> 0xFA7FFFFF[1.10] Temp BUS: 0xF1 -> 0xF1 | MMIOL: 0xFA900000 -> 0xFAFFFFFF[1.11] Temp BUS: 0xF6 -> 0xF6 | MMIOL: 0xFB100000 -> 0xFB7FFFFF
[1] IIO Early Link Training Starting...
Recipy decompressing...
Recipy decompressing...
Socket[1] Stack[1] Program RX recipe values START...
Program recipe revision 2.009 (Info : 1.5:, len 2966)
[1] Program RX recipe values END
Socket[1] Stack[2] Program RX recipe values START...
Program recipe revision 2.009 (Info : 1.5:, len 2966)
[1] Program RX recipe values END
Socket[1] Stack[3] Program RX recipe values START...
Program recipe revision 2.009 (Info : 1.5:, len 2966)
[1] Program RX recipe values END
Socket[1] Stack[4] Program RX recipe values START...
Program recipe revision 2.009 (Info : 1.5:, len 2966)
[1] Program RX recipe values END
Socket[1] Stack[5] Program RX recipe values START...
Program recipe revision 2.009 (Info : 1.5:, len 2966)
[1] Program RX recipe values END
Socket[1] Stack[6] Program RX recipe values START...
Program recipe revision 2.009 (Info : 1.5:, len 2966)
[1] Program RX recipe values END
CXL_IO_PRE_TRAIN_INIT_START
CXL_IO_PRE_TRAIN_INIT_END
FBLP_PRE_TRAIN_INIT_START
FBLP_PRE_TRAIN_INIT_END
[1] IIO Early Link Training Completed!
IIO CXL Status Socket 0:
[0.1] NotTrained
[0.2] NotTrained
[0.3] NotTrained
[0.4] NotSupportCxlMode
[0.5] NotSupportCxlMode
[0.6] NotSupportCxlMode
[0.7] NotSupportCxlMode
IIO CXL Status Socket 1:
[1.1] AlreadyInCxlMode
[1.2] NotTrained
[1.3] NotTrained
[1.4] NotSupportCxlMode
[1.5] NotSupportCxlMode
[1.6] NotSupportCxlMode
[1.7] NotSupportCxlMode
CXL_NOTIFY_PCODE_START
CXL_NOTIFY_PCODE_END
IIO Early Link Tc/Vc Configuration Start
Final Tc/VC mapping:
[0] Program TC/VC mapping on IIO side
[0] Program/Poll TC/VC mapping on PCH side
Poll TC/VC mapping on IIO side
IIO Early Link Tc/Vc Configuration End
Calling IioEarlyIntiazeEntry StopCXL: Port location: Socket=1, Stack=1CXL: Program the RCRB Bar.SetRcrbBar (): RcrbBase = 0xD1400000CXL: Program Secondary and Subordinate bus for DP.
Socket 1 Stack 1 Configure UP Rcrb start
Socket 1 Stack 1 Configure UP Rcrb endCXL: Enumerate CXL devices.
Serial number cap not found for Seg:0 Bus:98 Dev:0 Fun:0n
CXL: Allocate MMIO resource for CXL DP and UP.Program MEMBAR0 for CXL Downstream portWarning: Created a Memory Hole: 0xD1402000 ~ 0xD141FFFFMEMBAR0: Base = 0xD1420000, Size = 0x20000Program MEMBAR0 for CXL Upstream portMEMBAR0: Base = 0xD1500000, Size = 0x10000CXL: Collect and clear Error Status for RAS.CXL: Configure Security Policy.Read Cxl CapCXL: Configure the CXL.Arb-Mux Clock Gating Enable bitsCXL: Detect topology.******* Initialize CXL - END *******BIOS源码解析 Initialize CXL
// C:\work\src\MIntelSPRBIOS84D24\Intel\ServerSiliconPkg\Upi\Library\UncoreLib\KtiMain.c
KtiMain()KtiDebugPrintInfo0 ((KTI_DEBUG_INFO0, "%a******* Initialize CXL - %a *******\n", "\n\n", "START"));InitializeComputeExpressLink (&SocketData, &KtiInternalGlobal);// C:\work\src\MIntelSPRBIOS84D24\Intel\ServerSiliconPkg\Upi\Library\CxlLib\CxlLib.cKtiDebugPrintInfo0 ((KTI_DEBUG_INFO0, "\nCXL: IIO EarlyLink Init Start.\n"));IioEarlyLinkInit()// C:\work\src\MIntelSPRBIOS84D24\Intel\ServerSiliconPkg\Iio\Library\PeiIioInitLib\IioEarlyInitSpr.c//// Get HCX sub-system type//HcxType = GetHcxType (IioIndex);IIO_D_LOG ("HcxType[%d] = %a\n", IioIndex, ((HcxType == IIO_HCA) ? "HCA"...);IioDisableVmdForInit()IIO_D_VMDLOG ("[%d] VMD disabled for RPs init.\n", IioIndex);// Program MS2IOSF credits.// BIOS only programs credits when warm reset is not still issuedTriggerCreditsHwInit()// MaxIioStackNumber may be 12for (StackIndex = 0; StackIndex < MaxIioStackNumber; StackIndex++) {IIO_D_LOG ("Program HW_INIT using SB access\n"); // 9 times}PcieProgramBifurcationPerSocket()IioGlobalData->IioVar.IioOutData.IsSocketSmbEnabled[IioIndex] = TRUE;IIO_D_PCILOG ("[%d] Cpxsmb enabled\n", IioIndex);// Program MS2IOSF bank decodersProgramMs2IosfBankDecoder()ProgramMs2IosfBankDecoderBanks()IIO_D_LOG ("MS2IOSF_BANK_DECODER_INIT_START\n");// MS2IOSF BankDecoder: TableSize 119, Recipe Revision 1.16IIO_D_LOG ("MS2IOSF BankDecoder: TableSize %d, Recipe Revision %a\n", TableSize, BankDecoderVerGen2Ptr->Revision);IIO_D_LOG ("MS2IOSF_BANK_DECODER_INIT_END\n");// Scan and record the PCIe port visible// [0 p0] DMI device is enabledIioPreLinkDataInitPerSocket()// Dmi on SPR has no PCI device instance. Its PciePortConfig should be hard code to enabled.IioGlobalData->IioVar.IioOutData.PciePortConfig[(IioIndex * MaxPortNumberPerSocket) + PortIndex] = 0x01;IioGlobalData->IioVar.IioOutData.PciePortPresent[(IioIndex * MaxPortNumberPerSocket) + PortIndex] = 0x01;StsStrPtr = "enabled";IIO_D_PCILOG ("[%d p%d] DMI device is %a\n", IioIndex, PortIndex, StsStrPtr);// [0.1 p1] 00:15:01.0: PCI device 8086:352A is enabled// [0.1 p2] 00:15:02.0: PCI device FFFF:FFFF is disabled (not present)// [0.1 p3] 00:15:03.0: PCI device FFFF:FFFF is disabled (not present)// [0.5 p39] 00:59:07.0: PCI device 8086:352D is enabled// [0.5 p40] 00:59:08.0: PCI device FFFF:FFFF is disabled (not present)// 读设备VID, 不为全F 即使能IIO_D_PCILOG ("[%d.%d p%d] %02X:%02X:%02X.%X: PCI device %04X:%04X is %a\n", IioIndex, StackIndex, PortIndex,IioGlobalData->IioVar.IioVData.SegmentSocket[IioIndex], BusBase, Device, Function,IioPciExpressRead16 (IioIndex, BusBase, Device, Function, PCI_VENDOR_ID_OFFSET),IioPciExpressRead16 (IioIndex, BusBase, Device, Function, PCI_DEVICE_ID_OFFSET),StsStrPtr);// Execute IIO Configuration only if not reset is required.// with this we avoid to configure IIO in the first boot after flash BIOSIIO_D_LOG ("Calling IioEarlyIntiazeEntry Start\n");// C:\work\src\MIntelSPRBIOS84D24\Intel\ServerSiliconPkg\Iio\Library\PeiDxeCommonIioInitLib\IioEarlyInitializeSpr.cIioEarlyInitializeEntry()// [0] IioAllocateMmioResource: Seg=0, MaxStackPerSocket=12IioAllocateMmioResource()IIO_D_LOG ("[%d] %a: Seg=%d, MaxStackPerSocket=%d\n", IioIndex, __FUNCTION__, SegmentNum, MaxStackPerSocket);IIO_D_LOG (" [%d.%d] Temp BUS: 0x%02x -> 0x%02x | MMIOL: 0x%08x -> 0x%08x\n", IioIndex, StackIndex, StackBusBase, StackBusLimit, StackMmiolBase, StackMmiolLimit);// This API function is called in PEI Phase to assign MMIO resources(<4GB) to all PCI Devices blong to every IIO Stack.AssignMmio32_PciBusRange()IIO_D_LOG ("[%d] IIO Early Link Training Starting...\n", IioIndex);IioEarlyPreLinkTrainingPhase()DfxPcieInit ()// Apply IIO RX Recipe settings hereIioPhyRecipeInit()RecipeProgramming()IIO_D_PCILOG ("Socket[%d] Stack[%d] Program RX recipe values START...\n", IioIndex, StackIndex);IIO_D_PCILOG ("Program recipe revision %a (%a, len %d)\n", RecipeHdrTablePtr->Revision, RecipeHdrTablePtr->HelperString, RecipeHdrTablePtr->NumberEntries);IIO_D_PCILOG ("[%d] Program RX recipe values END\n", IioIndex);IioEarlyPcieLinkTrainingPhase()IioCxlIoPortPreTrainInit()IIO_D_LOG ("CXL_IO_PRE_TRAIN_INIT_START\n");IIO_D_LOG ("CXL_IO_PRE_TRAIN_INIT_END\n");FblpPreTrainInit()IIO_D_LOG ("FBLP_PRE_TRAIN_INIT_START\n");IIO_D_LOG ("FBLP_PRE_TRAIN_INIT_END\n");IIO_D_LOG ("[%d] IIO Early Link Training Completed!\n", IioIndex);// First poll link status after link trainingIioCxlDetectionAfterLinkTraining()CheckCxlCap()//// APNSTS 17:16 Alternate Protocol Negotiation Status// 00 - APN not enabled// 01 - APN enabled, but no link partner support (no modified TS exchange)// 10 - APN resulted in failed negotiation or no agreement// 11 - APN was successful//if(LtssmSts.Bits.apnsts == 3 || (IsSiliconWorkaroundEnabled ("S14011768962") &&IioGlobalData->SetupData.PcieSubSystemMode[IioIndex][IouIndex] == IIO_MODE_FORCE_CXL)) {{SetCxlStatus (IioIndex, StackIndex, AlreadyInCxlMode); // Report CXL enable to KTISetCxlBitMap (IioIndex, StackIndex);SetCxlConnected (IioIndex, StackIndex, TRUE, FALSE); // Report to the CXL 1.1/2.0 API as 1.1 connected...}DumpCxlStatus()IIO_D_PCILOG ("IIO CXL Status Socket %d:\n", IioIndex);for(0 : GetMaxIouNumPerSocket)IIO_D_PCILOG ("[%d.%d] %a\n", IioIndex, StackIndex, Enum2Name[EnumIndex]);// PEI enumeration of CXL devices.IioCxlEnumerate ();// Communicate to Pcode which PI5 instance is connected to CXL device.NotifyCxlInst (IioGlobalData);IIO_D_LOG ("CXL_NOTIFY_PCODE_START\n");IIO_D_LOG ("CXL_NOTIFY_PCODE_END\n");IIO_D_DMILOG ("IIO Early Link Tc/Vc Configuration Start\n");// Configure Dmi Tc/Vc// 5331816: [LBG Val Critical] After warm reset, ME11 access to UMA does not work immediately after DIDIioDmiTcVcSetup (IioGlobalData);// program TC/VC settings first on CPU side// next program and pollProgrammTcVcMapping()IIO_D_DMILOG ("[%d] Program TC/VC mapping on IIO side\n", IioIndex);IIO_D_DMILOG ("[%d] Program/Poll TC/VC mapping on PCH side\n", IioIndex);IIO_D_DMILOG ("Poll TC/VC mapping on IIO side\n");IIO_D_DMILOG ("IIO Early Link Tc/Vc Configuration End\n");// Review CXL.cache limitationsIioCxlCheckCacheLimits()IIO_D_LOG ("Calling IioEarlyIntiazeEntry Stop\n"); // C:\work\src\MIntelSPRBIOS84D24\Intel\ServerSiliconPkg\Upi\Library\CxlLib\CxlLib.c// InitializeComputeExpressLinkSpr detecs CXL11 enabled stacks and configure CXL uncore parameters.// If CXL EP device supports cxl cache protocol, cache protocol enabled in bridges and EP devices.InitializeComputeExpressLinkSpr (SocketData, KtiInternalGlobal);KtiDebugPrintInfo0 ((KTI_DEBUG_INFO0, "\n\nCXL: Port location: Socket=%X, Stack=%X\n", SocketId, StackId));KtiDebugPrintInfo0 ((KTI_DEBUG_INFO0, "\nCXL: Program the RCRB Bar.\n"));SetRcrbBar()DEBUG ((DEBUG_ERROR, " %a (): RcrbBase = 0x%08X\n", __FUNCTION__, BarAddr));/*Routine to program the CLX RCRB BAR for the specified CLX enabled stackThis function performs 3 different operations.1. Programs RCRB register2. Programs Secondary and Subordinate Bus numbers for DP3. Indirectly programs UP RCRB by issuing memory access operation.Refer CXL 1.1 Rev. 1.1 Section 7.2.1.2. "the upstream port captures theupper address bits[63:12] of the first memory access received after linktraining as the base address for the upstream port RCRB"*/ProgramCXLRcrbBar()KtiDebugPrintInfo0 ((KTI_DEBUG_INFO0, "\nCXL: Program Secondary and Subordinate bus for DP.\n"));KtiDebugPrintInfo0 ((KTI_DEBUG_INFO0, "Socket %d Stack %d Configure UP Rcrb start\n", Socket, Stack));KtiDebugPrintInfo0 ((KTI_DEBUG_INFO0, "Socket %d Stack %d Configure UP Rcrb end\n", Socket, Stack));KtiDebugPrintInfo0 ((KTI_DEBUG_INFO0, "\nCXL: Enumerate CXL devices.\n"));EnumerateCxlDevice()EnumerateCxlDeviceCxl20DevCmpat()GetCxlDevSerialNum()GetPciDevSerialNum()// Serial number cap not found for Seg:0 Bus:98 Dev:0 Fun:0nDEBUG ((DEBUG_ERROR, "Serial number cap not found for Seg:%d Bus:%x Dev:%d Fun:%dn", CpuCsrAccessVarPtr->segmentSocket[Seg], Bus, Dev, Fun));KtiDebugPrintInfo0 ((KTI_DEBUG_INFO0, "\nCXL: Allocate MMIO resource for CXL DP and UP.\n"));AllocateMmioForCxlPort()AllocateMmioForCxlPortCxl20DevCmpat()KtiDebugPrintInfo1 ((KTI_DEBUG_INFO1, "\n Program MEMBAR0 for CXL Downstream port\n"));ProgramMemBar0Register()// Adjust the MMIO base address to meet the alignment//// Warning: Created a Memory Hole: 0xD1402000 ~ 0xD141FFFF// MEMBAR0: Base = 0xD1420000, Size = 0x20000//*MemBar0Base = (MmioStartAddr + *MemBar0Size - 1) & (~(*MemBar0Size - 1));if ((UINT64) MmioStartAddr != *MemBar0Base) {DEBUG ((DEBUG_ERROR, " Warning: Created a Memory Hole: 0x%x ~ 0x%x\n", MmioStartAddr, *MemBar0Base - 1));}DEBUG ((DEBUG_ERROR, " MEMBAR0: Base = 0x%lx, Size = 0x%lx\n", *MemBar0Base, *MemBar0Size));KtiDebugPrintInfo0 ((KTI_DEBUG_INFO0, "\nCXL: Collect and clear Error Status for RAS.\n"));KtiDebugPrintInfo0 ((KTI_DEBUG_INFO0, "\nCXL: Configure Security Policy.\n"));KtiDebugPrintInfo0 ((KTI_DEBUG_INFO0, "\nRead Cxl Cap\n"));KtiDebugPrintInfo0 ((KTI_DEBUG_INFO0, "\nCXL: Configure the CXL.Arb-Mux Clock Gating Enable bits\n"));KtiDebugPrintInfo0 ((KTI_DEBUG_INFO0, "\nCXL: Detect topology.\n"));KtiDebugPrintInfo0 ((KTI_DEBUG_INFO0, "%a******* Initialize CXL - %a *******\n", "\n", "END ")CXL Memory Map BIOS 打印
***BEGIN MEMORY MAPPING***
mmiohbasefrom setup: 2000 MMIOH base = 80000 (64mb)
PMem mgmt Driver is available..
CXL: Socket 0 Stack 0, CXL device not found
...
Serial number cap not found for Seg:0 Bus:98 Dev:0 Fun:0nGetCxlEndDeviceInfo CXL: Socket 1 Stack 1 Instance 0, 0
CXL: Socket 1 Stack 1, Read CXL NDR+DRS mode cap, Status Success Cap 1
CXL: Socket 1 Stack 1, Enable CXL NDR+DRS mode DVSEC, Status Success
CXL: Socket 1 Stack 1 memory expander is supported in CXL type2 flowDOE status reg-0x0DOE status reg-0x80000003DOE status reg-0x80000003DOE status reg-0x80000003...
CXL: Socket 1 Stack 1, Get CDAT info for CXL device segment 0 bus 152 status Success.DOE status reg-0x2DOE status reg-0x80000003DOE status reg-0x80000003DOE status reg-0x80000003DOE status reg-0x80000003DOE status reg-0x80000003DOE status reg-0x80000003DOE status reg-0x80000003...
CXL CDAT Raw Data in Hex:
A0 00 00 00 01 2B 00 00 00 00 00 00 00 00 00 00
00 00 18 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 04 00 00 00 01 00 18 00 00 00 01 00
E8 03 00 00 00 00 00 00 20 00 20 00 10 00 00 00
01 00 18 00 00 00 02 00 E8 03 00 00 00 00 00 00
20 00 20 00 10 00 00 00 01 00 18 00 00 00 04 00
E8 03 00 00 00 00 00 00 18 00 00 00 10 00 00 00
01 00 18 00 00 00 05 00 E8 03 00 00 00 00 00 00
0C 00 00 00 08 00 00 00 04 00 18 00 00 00 00 00
00 00 00 00 01 00 00 00 00 00 00 00 03 00 00 00DOE status reg-0x2DOE status reg-0x80000003DOE status reg-0x80000003DOE status reg-0x80000003DOE status reg-0x2。。。VolMemPerf: RdLat = 320(100ps), WrLat = 320(100ps), RdBw = 240(100MB/s), WrBw = 120(100MB/s) - ValidPerMemPerf: RdLat = 0(100ps), WrLat = 0(100ps), RdBw = 0(100MB/s), WrBw = 0(100MB/s) - InvalidDOE status reg-0x2DOE status reg-0x80000003DOE status reg-0x80000003DOE status reg-0x80000003。。。
CXL: Socket 1 Stack 1, Get CDAT info for CXL device segment 0 bus 152 status Success.DOE status reg-0x2DOE status reg-0x80000003DOE status reg-0x80000003DOE status reg-0x80000003DOE status reg-0x80000003DOE status reg-0x80000003DOE status reg-0x80000003DOE status reg-0x80000003。。。
CXL: GetCxlHdmDecoderCapability start
CXL: GetCxlHdmDecoderCapRegister start
CXL: No CXL HDM decode capability found
CXL: Socket 1 Stack 1, CXL HDM decoder capability is N/A
...
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^Platform CXL Memory Configuration
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Socket Stack VID Type S/N Status Size1 GSB1 MT1 DI1 Size2 GSB2 MT2 DI21 1 1B00 Exp 0 0 C0 0 0 0 - - - -
N0.C00.D0.R0: ranksize = 200, NVranksize = 0 (rank enabled)
N0.C00.D0.R1: ranksize = 200, NVranksize = 0 (rank enabled)
N1.C00.D0.R0: ranksize = 200, NVranksize = 0 (rank enabled)
N1.C00.D0.R1: ranksize = 200, NVranksize = 0 (rank enabled)
N0: Total mem size = 1024; mem size = 1024; per size = 0
N1: Total mem size = 2048; mem size = 1024; per size = 0
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^BIOS源码解析 Memory Map
InitMemoryMap()RcDebugPrintWithDevice (SDBG_MAX, NO_SOCKET, NO_CH, NO_DIMM, NO_SUBCH, NO_RANK, NO_STROBE, NO_BIT, "\n***BEGIN MEMORY MAPPING***\n");// Initialize paramaters for memory mapping only for MEM_MAP_STATE_RESOURCE_CALCULATION// This routine initializes memory mapping parameters based on setup options and system capability.InitMemMapParams()RcDebugPrintWithDevice (SDBG_MAX, NO_SOCKET, NO_CH, NO_DIMM, NO_SUBCH, NO_RANK, NO_STROBE, NO_BIT,"mmiohbasefrom setup: %x MMIOH base = %x (64mb)\n", MmiohBaseSetup , MemMapHost->mmiohBase);// Populate DDRT structures and partition DIMMsEvaluateAndPartitionDdrt()RcDebugPrintWithDevice (SDBG_MAX, NO_SOCKET, NO_CH, NO_DIMM, NO_SUBCH, NO_RANK, NO_STROBE, NO_BIT,"PMem mgmt Driver is available..\n");// This routine initializes the memory size fields in the structures for DIMMs, Channels, and Nodes.PopulateMemorySizeFields()// This function scans through all enabled sockets to discover CXL devices and constructs CXL topology in memory map private data structure.DiscoverCxlDevices()// This function scans all enabled sockets for CXL memory devices.PopulateCxlMemDevices()// This function gets the information of specified CXL end deviceGetCxlEndDeviceInfo()// Get the DVSEC register data of CXL memory device.GetCxlMemDeviceRegData()if (GetCxlStatus (ScktId, StackId) != AlreadyInCxlMode) {RcDebugPrint (SDBG_MINMAX, "CXL: Socket %d Stack %d, CXL device not found\n", ScktId, StackId);return EFI_UNSUPPORTED;}// Get the S/N and VID pair of CXL node.GetCxlEndDevIdentifiers()GetCxlDevSerialNum()GetPciDevSerialNum()// Serial number cap not found for Seg:0 Bus:98 Dev:0 Fun:0DEBUG ((DEBUG_ERROR, "Serial number cap not found for Seg:%d Bus:%x Dev:%d Fun:%dn")RcDebugPrint (SDBG_MAX, "%a CXL: Socket %d Stack %d Instance %d, Serial number: %lx, Vendor ID: %x\n",__FUNCTION__,ScktId,StackId,InstanceId,CxlEndDevInfo->CxlNodeCommonInfo.SerialNumber,CxlEndDevInfo->CxlNodeCommonInfo.VendorId);CxlEndDevInfo->HdmCount = (UINT8) CxlDeviceCapability->Bits.HdmCount;CxlEndDevInfo->MemHwInitMode = (BOOLEAN) CxlDeviceCapability->Bits.MemHwInitMode;CxlCacheCapable = (BOOLEAN) CxlDeviceCapability->Bits.CacheCapable;IsNdrDrsModeCapabable()// CXL: Socket 1 Stack 1, Read CXL NDR+DRS mode cap, Status Success Cap 1// CXL: Socket 1 Stack 1, Enable CXL NDR+DRS mode DVSEC, Status SuccessRcDebugPrint (SDBG_MINMAX, "CXL: Socket %d Stack %d, Read CXL NDR+DRS mode cap, Status %r Cap %d\n", ScktId, StackId, Status, Cap);RcDebugPrint (SDBG_MINMAX, "CXL: Socket %d Stack %d, Enable CXL NDR+DRS mode DVSEC, Status %r\n", ScktId, StackId, Status);RcDebugPrint(SDBG_MINMAX, "CXL: Socket %d Stack %d memory expander is supported in CXL type2 flow\n", ScktId, StackId);CxlEndDevInfo->MemExpander = TRUE;// Check if CXL CDAT data is valid when CXL CDAT is present.CheckCxlCdatData()GetCxlEndDevCdat()GetCdatTableSize()... DEBUG ((DEBUG_ERROR, "\tDOE status reg-0x%x\n", StsReg.Data32));// CXL: Socket 1 Stack 1, Get CDAT info for CXL device segment 0 bus 152 status Success.RcDebugPrint (SDBG_MINMAX, "CXL: Socket %d Stack %d, Get CDAT info for CXL device segment %d bus %d status %r.\n", ScktId, StackId, Segment, Bus, Status);// Dump the raw data of CXL CDAT buffer.DisplayCxlCdatRawData()// Get the memory information of CXL end device.GetCxlEndDevMemInfo()// Parse the information data of CXL memory.// 计算基地址、大小、属性、媒介类型// This function gets the information of CXL memory within the specified HDM range from the CDAT of the specified CXL end device.GetCxlMemInfoFromCdat()// 读取设备 CDAT ,解析大小// Range 0: VolCap = 0x000000C0(64MB), PerCap = 0x00000000(64MB), DesiredInterleave = 0x000RcDebugPrint (SDBG_MAX, "Range %d: VolCap = 0x%08x(64MB), PerCap = 0x%08x(64MB), DesiredInterleave = 0x%03x\n",HdmId,CxlEndDevInfo->CxlMemInfo[HdmId].VolCap,CxlEndDevInfo->CxlMemInfo[HdmId].PerCap,CxlEndDevInfo->CxlMemInfo[HdmId].DesiredInterleave);GetCxlEndDevPerfData()DisplayCxlEndDevPerfData()// VolMemPerf: RdLat = 320(100ps), WrLat = 320(100ps), RdBw = 240(100MB/s), WrBw = 120(100MB/s) - Valid// PerMemPerf: RdLat = 0(100ps), WrLat = 0(100ps), RdBw = 0(100MB/s), WrBw = 0(100MB/s) - InvalidRcDebugPrint (SDBG_MAX, " VolMemPerf: RdLat = %d(100ps), WrLat = %d(100ps), RdBw = %d(100MB/s), WrBw = %d(100MB/s) - %a\n",...)RcDebugPrint (SDBG_MAX, " PerMemPerf: RdLat = %d(100ps), WrLat = %d(100ps), RdBw = %d(100MB/s), WrBw = %d(100MB/s) - %a\n",...)// Get the CXL end device miscellaneous informationGetCxlEndDevInfoMisc() GetCxlDevHdmDecoderCap()GetCxlHdmDecoderCapability()RcDebugPrint (SDBG_MINMAX, "CXL: %a start\n", __FUNCTION__);GetCxlHdmDecoderCapRegister()RcDebugPrint (SDBG_MINMAX, "CXL: %a start\n", __FUNCTION__);if (CapHdrReg.Bits.ArraySize == 0) {RcDebugPrint (SDBG_MINMAX, "CXL: No CXL capabilities found\n");return EFI_UNSUPPORTED; }RcDebugPrint (SDBG_MINMAX, "CXL: Socket %d Stack %d, CXL HDM decoder capability is N/A\n", ScktId, StackId);PrintCxlMemDevices()RcDebugPrint (SDBG_MAX, " Platform CXL Memory Configuration\n");...BIOS_CXL_INIT_FLOW相关推荐
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